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Ilko Iliev32949232009-06-12 21:20:39 +02001/*
2 * (C) Copyright 2007-2008
Stelian Popc9e798d2011-11-01 00:00:39 +01003 * Stelian Pop <stelian@popies.net>
Ilko Iliev32949232009-06-12 21:20:39 +02004 * Lead Tech Design <www.leadtechdesign.com>
5 * Ilko Iliev <www.ronetix.at>
6 *
7 * Configuation settings for the RONETIX PM9261 board.
8 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02009 * SPDX-License-Identifier: GPL-2.0+
Ilko Iliev32949232009-06-12 21:20:39 +020010 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
Asen Dimovf47316a2011-07-26 04:48:41 +000015/*
16 * SoC must be defined first, before hardware.h is included.
17 * In this case SoC is defined in boards.cfg.
18 */
19
20#include <asm/hardware.h>
Ilko Iliev32949232009-06-12 21:20:39 +020021/* ARM asynchronous clock */
Ilko Iliev32949232009-06-12 21:20:39 +020022
Ilko Iliev32949232009-06-12 21:20:39 +020023#define MASTER_PLL_DIV 15
24#define MASTER_PLL_MUL 162
25#define MAIN_PLL_DIV 2
Asen Dimovf47316a2011-07-26 04:48:41 +000026#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
Achim Ehrlich7c966a82010-02-24 10:29:16 +010027#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
Ilko Iliev32949232009-06-12 21:20:39 +020028
Asen Dimovf47316a2011-07-26 04:48:41 +000029#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261"
Ilko Iliev32949232009-06-12 21:20:39 +020030#define CONFIG_PM9261 1 /* on a Ronetix PM9261 Board */
31#define CONFIG_ARCH_CPU_INIT
Asen Dimov4f81bf42010-12-12 12:41:30 +020032#define CONFIG_SYS_TEXT_BASE 0
Ilko Iliev32949232009-06-12 21:20:39 +020033
Asen Dimova3e09cc2011-10-31 08:54:20 +000034#define MACH_TYPE_PM9261 1187
35#define CONFIG_MACH_TYPE MACH_TYPE_PM9261
36
Ilko Iliev32949232009-06-12 21:20:39 +020037/* clocks */
38/* CKGR_MOR - enable main osc. */
39#define CONFIG_SYS_MOR_VAL \
Asen Dimove3150c72010-04-06 16:18:04 +030040 (AT91_PMC_MOR_MOSCEN | \
Ilko Iliev32949232009-06-12 21:20:39 +020041 (255 << 8)) /* Main Oscillator Start-up Time */
42#define CONFIG_SYS_PLLAR_VAL \
Asen Dimove3150c72010-04-06 16:18:04 +030043 (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
44 AT91_PMC_PLLXR_OUT(3) | \
Ilko Iliev32949232009-06-12 21:20:39 +020045 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
46
47/* PCK/2 = MCK Master Clock from PLLA */
48#define CONFIG_SYS_MCKR1_VAL \
Asen Dimove3150c72010-04-06 16:18:04 +030049 (AT91_PMC_MCKR_CSS_SLOW | \
50 AT91_PMC_MCKR_PRES_1 | \
Bo Shen7ac2e7c2013-11-15 11:12:33 +080051 AT91_PMC_MCKR_MDIV_2)
Ilko Iliev32949232009-06-12 21:20:39 +020052
53/* PCK/2 = MCK Master Clock from PLLA */
54#define CONFIG_SYS_MCKR2_VAL \
Asen Dimove3150c72010-04-06 16:18:04 +030055 (AT91_PMC_MCKR_CSS_PLLA | \
56 AT91_PMC_MCKR_PRES_1 | \
Bo Shen7ac2e7c2013-11-15 11:12:33 +080057 AT91_PMC_MCKR_MDIV_2)
Ilko Iliev32949232009-06-12 21:20:39 +020058
59/* define PDC[31:16] as DATA[31:16] */
60#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
61/* no pull-up for D[31:16] */
62#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000
63
64/* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
65#define CONFIG_SYS_MATRIX_EBICSA_VAL \
Asen Dimove3150c72010-04-06 16:18:04 +030066 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A)
Ilko Iliev32949232009-06-12 21:20:39 +020067
68/* SDRAM */
69/* SDRAMC_MR Mode register */
70#define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL
71/* SDRAMC_TR - Refresh Timer register */
72#define CONFIG_SYS_SDRC_TR_VAL1 0x13C
73/* SDRAMC_CR - Configuration register*/
74#define CONFIG_SYS_SDRC_CR_VAL \
75 (AT91_SDRAMC_NC_9 | \
76 AT91_SDRAMC_NR_13 | \
77 AT91_SDRAMC_NB_4 | \
78 AT91_SDRAMC_CAS_3 | \
79 AT91_SDRAMC_DBW_32 | \
80 (1 << 8) | /* Write Recovery Delay */ \
81 (7 << 12) | /* Row Cycle Delay */ \
82 (3 << 16) | /* Row Precharge Delay */ \
83 (2 << 20) | /* Row to Column Delay */ \
84 (5 << 24) | /* Active to Precharge Delay */ \
85 (1 << 28)) /* Exit Self Refresh to Active Delay */
86
87/* Memory Device Register -> SDRAM */
88#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
89#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
90#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
91#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
92#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
93#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
94#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
95#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
96#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
97#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
98#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
99#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
100#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
101#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
102#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
103#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
104#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
105#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
106
107/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
108#define CONFIG_SYS_SMC0_SETUP0_VAL \
Asen Dimove3150c72010-04-06 16:18:04 +0300109 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
110 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
Ilko Iliev32949232009-06-12 21:20:39 +0200111#define CONFIG_SYS_SMC0_PULSE0_VAL \
Asen Dimove3150c72010-04-06 16:18:04 +0300112 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
113 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
Ilko Iliev32949232009-06-12 21:20:39 +0200114#define CONFIG_SYS_SMC0_CYCLE0_VAL \
Asen Dimove3150c72010-04-06 16:18:04 +0300115 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
Ilko Iliev32949232009-06-12 21:20:39 +0200116#define CONFIG_SYS_SMC0_MODE0_VAL \
Asen Dimove3150c72010-04-06 16:18:04 +0300117 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
118 AT91_SMC_MODE_DBW_16 | \
119 AT91_SMC_MODE_TDF | \
120 AT91_SMC_MODE_TDF_CYCLE(6))
Ilko Iliev32949232009-06-12 21:20:39 +0200121
122/* user reset enable */
123#define CONFIG_SYS_RSTC_RMR_VAL \
124 (AT91_RSTC_KEY | \
Asen Dimove3150c72010-04-06 16:18:04 +0300125 AT91_RSTC_CR_PROCRST | \
126 AT91_RSTC_MR_ERSTL(1) | \
127 AT91_RSTC_MR_ERSTL(2))
Ilko Iliev32949232009-06-12 21:20:39 +0200128
129/* Disable Watchdog */
130#define CONFIG_SYS_WDTC_WDMR_VAL \
Asen Dimove3150c72010-04-06 16:18:04 +0300131 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
132 AT91_WDT_MR_WDV(0xfff) | \
133 AT91_WDT_MR_WDDIS | \
134 AT91_WDT_MR_WDD(0xfff))
Ilko Iliev32949232009-06-12 21:20:39 +0200135
136#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
137#define CONFIG_SETUP_MEMORY_TAGS 1
138#define CONFIG_INITRD_TAG 1
139
140#undef CONFIG_SKIP_LOWLEVEL_INIT
Asen Dimov0160c1e2011-12-09 10:59:07 +0000141#define CONFIG_BOARD_EARLY_INIT_F
Ilko Iliev32949232009-06-12 21:20:39 +0200142
143/*
144 * Hardware drivers
145 */
Jens Scharsigea8fbba2010-02-03 22:46:16 +0100146#define CONFIG_AT91_GPIO 1
Ilko Iliev32949232009-06-12 21:20:39 +0200147#define CONFIG_ATMEL_USART 1
Asen Dimovf47316a2011-07-26 04:48:41 +0000148#define CONFIG_USART_BASE ATMEL_BASE_DBGU
149#define CONFIG_USART_ID ATMEL_ID_SYS
Ilko Iliev32949232009-06-12 21:20:39 +0200150
151/* LCD */
Ilko Iliev32949232009-06-12 21:20:39 +0200152#define LCD_BPP LCD_COLOR8
153#define CONFIG_LCD_LOGO 1
154#undef LCD_TEST_PATTERN
155#define CONFIG_LCD_INFO 1
156#define CONFIG_LCD_INFO_BELOW_LOGO 1
157#define CONFIG_SYS_WHITE_ON_BLACK 1
158#define CONFIG_ATMEL_LCD 1
159#define CONFIG_ATMEL_LCD_BGR555 1
Ilko Iliev32949232009-06-12 21:20:39 +0200160
161/* LED */
162#define CONFIG_AT91_LED
Andreas Bießmannbcf9fe32013-11-29 12:13:46 +0100163#define CONFIG_RED_LED GPIO_PIN_PC(12)
164#define CONFIG_GREEN_LED GPIO_PIN_PC(13)
165#define CONFIG_YELLOW_LED GPIO_PIN_PC(15)
Ilko Iliev32949232009-06-12 21:20:39 +0200166
Ilko Iliev32949232009-06-12 21:20:39 +0200167
168/*
169 * BOOTP options
170 */
171#define CONFIG_BOOTP_BOOTFILESIZE 1
172#define CONFIG_BOOTP_BOOTPATH 1
173#define CONFIG_BOOTP_GATEWAY 1
174#define CONFIG_BOOTP_HOSTNAME 1
175
176/*
177 * Command line configuration.
178 */
Ilko Iliev32949232009-06-12 21:20:39 +0200179#define CONFIG_CMD_NAND 1
Ilko Iliev32949232009-06-12 21:20:39 +0200180
181/* SDRAM */
182#define CONFIG_NR_DRAM_BANKS 1
183#define PHYS_SDRAM 0x20000000
184#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
185
186/* DataFlash */
187#define CONFIG_ATMEL_DATAFLASH_SPI
188#define CONFIG_HAS_DATAFLASH
Ilko Iliev32949232009-06-12 21:20:39 +0200189#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
190#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
191#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* CS3 */
192#define AT91_SPI_CLK 15000000
193#define DATAFLASH_TCSS (0x1a << 16)
194#define DATAFLASH_TCHS (0x1 << 24)
195
196/* NAND flash */
197#define CONFIG_NAND_ATMEL
Ilko Iliev32949232009-06-12 21:20:39 +0200198#define CONFIG_SYS_MAX_NAND_DEVICE 1
199#define CONFIG_SYS_NAND_BASE 0x40000000
200#define CONFIG_SYS_NAND_DBW_8 1
201/* our ALE is AD22 */
202#define CONFIG_SYS_NAND_MASK_ALE (1 << 22)
203/* our CLE is AD21 */
204#define CONFIG_SYS_NAND_MASK_CLE (1 << 21)
Andreas Bießmannac45bb12013-11-29 12:13:45 +0100205#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
206#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(16)
Ilko Iliev32949232009-06-12 21:20:39 +0200207
Ilko Iliev32949232009-06-12 21:20:39 +0200208/* NOR flash */
209#define CONFIG_SYS_FLASH_CFI 1
210#define CONFIG_FLASH_CFI_DRIVER 1
211#define PHYS_FLASH_1 0x10000000
212#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
213#define CONFIG_SYS_MAX_FLASH_SECT 256
214#define CONFIG_SYS_MAX_FLASH_BANKS 1
215
216/* Ethernet */
217#define CONFIG_DRIVER_DM9000 1
218#define CONFIG_DM9000_BASE 0x30000000
219#define DM9000_IO CONFIG_DM9000_BASE
220#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
221#define CONFIG_DM9000_USE_16BIT 1
222#define CONFIG_NET_RETRY_COUNT 20
223#define CONFIG_RESET_PHY_R 1
Ilko Iliev32949232009-06-12 21:20:39 +0200224
225/* USB */
226#define CONFIG_USB_ATMEL
Bo Shendcd2f1a2013-10-21 16:14:00 +0800227#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
Ilko Iliev32949232009-06-12 21:20:39 +0200228#define CONFIG_USB_OHCI_NEW 1
229#define CONFIG_DOS_PARTITION 1
230#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
231#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
232#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261"
233#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
Ilko Iliev32949232009-06-12 21:20:39 +0200234
235#define CONFIG_SYS_LOAD_ADDR 0x22000000
236
237#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
238#define CONFIG_SYS_MEMTEST_END 0x23e00000
239
240#undef CONFIG_SYS_USE_DATAFLASH_CS0
241#undef CONFIG_SYS_USE_NANDFLASH
242#define CONFIG_SYS_USE_FLASH 1
243
244#ifdef CONFIG_SYS_USE_DATAFLASH_CS0
245
246/* bootstrap + u-boot + env + linux in dataflash on CS0 */
247#define CONFIG_ENV_IS_IN_DATAFLASH 1
248#define CONFIG_SYS_MONITOR_BASE \
249 (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
250#define CONFIG_ENV_OFFSET 0x4200
251#define CONFIG_ENV_ADDR \
252 (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
253#define CONFIG_ENV_SIZE 0x4200
254#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
255#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
256 "root=/dev/mtdblock0 " \
Albin Tonnerre918319c2009-07-22 18:30:03 +0200257 "mtdparts=atmel_nand:-(root) " \
Ilko Iliev32949232009-06-12 21:20:39 +0200258 "rw rootfstype=jffs2"
259
260#elif defined(CONFIG_SYS_USE_NANDFLASH) /* CONFIG_SYS_USE_NANDFLASH */
261
262/* bootstrap + u-boot + env + linux in nandflash */
263#define CONFIG_ENV_IS_IN_NAND 1
264#define CONFIG_ENV_OFFSET 0x60000
265#define CONFIG_ENV_OFFSET_REDUND 0x80000
266#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
267#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
268#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
269 "root=/dev/mtdblock5 " \
Albin Tonnerre918319c2009-07-22 18:30:03 +0200270 "mtdparts=atmel_nand:128k(bootstrap)ro," \
Ilko Iliev32949232009-06-12 21:20:39 +0200271 "256k(uboot)ro,128k(env1)ro," \
272 "128k(env2)ro,2M(linux),-(root) " \
273 "rw rootfstype=jffs2"
274
275#elif defined (CONFIG_SYS_USE_FLASH)
276
277#define CONFIG_ENV_IS_IN_FLASH 1
278#define CONFIG_ENV_OFFSET 0x40000
279#define CONFIG_ENV_SECT_SIZE 0x10000
280#define CONFIG_ENV_SIZE 0x10000
281#define CONFIG_ENV_OVERWRITE 1
282
283/* JFFS Partition offset set */
284#define CONFIG_SYS_JFFS2_FIRST_BANK 0
285#define CONFIG_SYS_JFFS2_NUM_BANKS 1
286
287/* 512k reserved for u-boot */
288#define CONFIG_SYS_JFFS2_FIRST_SECTOR 11
289
290#define CONFIG_BOOTCOMMAND "run flashboot"
291
292#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=nand"
293#define MTDPARTS_DEFAULT \
294 "mtdparts=physmap-flash.0:" \
295 "256k(u-boot)ro," \
296 "64k(u-boot-env)ro," \
297 "1408k(kernel)," \
298 "-(rootfs);" \
299 "nand:-(nand)"
300
301#define CONFIG_CON_ROT "fbcon=rotate:3 "
302#define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 " CONFIG_CON_ROT
303
304#define CONFIG_EXTRA_ENV_SETTINGS \
305 "mtdids=" MTDIDS_DEFAULT "\0" \
306 "mtdparts=" MTDPARTS_DEFAULT "\0" \
307 "partition=nand0,0\0" \
308 "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
309 "nfsargs=setenv bootargs root=/dev/nfs rw " \
310 CONFIG_CON_ROT \
311 "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \
312 "addip=setenv bootargs $(bootargs) " \
313 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
314 ":$(hostname):eth0:off\0" \
315 "ramboot=tftpboot 0x22000000 vmImage;" \
316 "run ramargs;run addip;bootm 22000000\0" \
317 "nfsboot=tftpboot 0x22000000 vmImage;" \
318 "run nfsargs;run addip;bootm 22000000\0" \
319 "flashboot=run ramargs;run addip;bootm 0x10050000\0" \
320 ""
321#else
322#error "Undefined memory device"
323#endif
324
325#define CONFIG_BAUDRATE 115200
Ilko Iliev32949232009-06-12 21:20:39 +0200326
Ilko Iliev32949232009-06-12 21:20:39 +0200327#define CONFIG_SYS_CBSIZE 256
328#define CONFIG_SYS_MAXARGS 16
329#define CONFIG_SYS_PBSIZE \
330 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
331#define CONFIG_SYS_LONGHELP 1
332#define CONFIG_CMDLINE_EDITING 1
333
Ilko Iliev32949232009-06-12 21:20:39 +0200334/*
335 * Size of malloc() pool
336 */
337#define CONFIG_SYS_MALLOC_LEN \
338 ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
Ilko Iliev32949232009-06-12 21:20:39 +0200339
Asen Dimov4f81bf42010-12-12 12:41:30 +0200340#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
341#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
342 GENERATED_GBL_DATA_SIZE)
343
Ilko Iliev32949232009-06-12 21:20:39 +0200344#endif