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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 899590816a498beb771bc85f96a019cc91bcab3d / . / arch / arm / cpu / tegra20-common / pinmux.c
blob: 08b83055dbb74b4e660c3865e4930a04f41049c8 [file] [log] [blame]
Simon Glass858bd092011-08-30 06:23:14 +0000[diff] [blame]1/*
2 * Copyright (c) 2011 The Chromium OS Authors.
3 * See file CREDITS for list of people who contributed to this
4 * project.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
21
Allen Martin00a27492012-08-31 08:30:00 +0000[diff] [blame]22/* Tegra20 pin multiplexing functions */
Simon Glass858bd092011-08-30 06:23:14 +0000[diff] [blame]23
Simon Glass858bd092011-08-30 06:23:14 +0000[diff] [blame]24#include <common.h>
Tom Warren150c2492012-09-19 15:50:56 -0700[diff] [blame]25#include <asm/io.h>
26#include <asm/arch/tegra.h>
27#include <asm/arch/pinmux.h>
Simon Glass858bd092011-08-30 06:23:14 +0000[diff] [blame]28
29
Simon Glass20e18e02011-09-21 12:40:06 +0000[diff] [blame]30/*
31 * This defines the order of the pin mux control bits in the registers. For
32 * some reason there is no correspendence between the tristate, pin mux and
33 * pullup/pulldown registers.
34 */
35enum pmux_ctlid {
36 /* 0: APB_MISC_PP_PIN_MUX_CTL_A_0 */
37 MUXCTL_UAA,
38 MUXCTL_UAB,
39 MUXCTL_UAC,
40 MUXCTL_UAD,
41 MUXCTL_UDA,
42 MUXCTL_RESERVED5,
43 MUXCTL_ATE,
44 MUXCTL_RM,
45
46 MUXCTL_ATB,
47 MUXCTL_RESERVED9,
48 MUXCTL_ATD,
49 MUXCTL_ATC,
50 MUXCTL_ATA,
51 MUXCTL_KBCF,
52 MUXCTL_KBCE,
53 MUXCTL_SDMMC1,
54
55 /* 16: APB_MISC_PP_PIN_MUX_CTL_B_0 */
56 MUXCTL_GMA,
57 MUXCTL_GMC,
58 MUXCTL_HDINT,
59 MUXCTL_SLXA,
60 MUXCTL_OWC,
61 MUXCTL_SLXC,
62 MUXCTL_SLXD,
63 MUXCTL_SLXK,
64
65 MUXCTL_UCA,
66 MUXCTL_UCB,
67 MUXCTL_DTA,
68 MUXCTL_DTB,
69 MUXCTL_RESERVED28,
70 MUXCTL_DTC,
71 MUXCTL_DTD,
72 MUXCTL_DTE,
73
74 /* 32: APB_MISC_PP_PIN_MUX_CTL_C_0 */
75 MUXCTL_DDC,
76 MUXCTL_CDEV1,
77 MUXCTL_CDEV2,
78 MUXCTL_CSUS,
79 MUXCTL_I2CP,
80 MUXCTL_KBCA,
81 MUXCTL_KBCB,
82 MUXCTL_KBCC,
83
84 MUXCTL_IRTX,
85 MUXCTL_IRRX,
86 MUXCTL_DAP1,
87 MUXCTL_DAP2,
88 MUXCTL_DAP3,
89 MUXCTL_DAP4,
90 MUXCTL_GMB,
91 MUXCTL_GMD,
92
93 /* 48: APB_MISC_PP_PIN_MUX_CTL_D_0 */
94 MUXCTL_GME,
95 MUXCTL_GPV,
96 MUXCTL_GPU,
97 MUXCTL_SPDO,
98 MUXCTL_SPDI,
99 MUXCTL_SDB,
100 MUXCTL_SDC,
101 MUXCTL_SDD,
102
103 MUXCTL_SPIH,
104 MUXCTL_SPIG,
105 MUXCTL_SPIF,
106 MUXCTL_SPIE,
107 MUXCTL_SPID,
108 MUXCTL_SPIC,
109 MUXCTL_SPIB,
110 MUXCTL_SPIA,
111
112 /* 64: APB_MISC_PP_PIN_MUX_CTL_E_0 */
113 MUXCTL_LPW0,
114 MUXCTL_LPW1,
115 MUXCTL_LPW2,
116 MUXCTL_LSDI,
117 MUXCTL_LSDA,
118 MUXCTL_LSPI,
119 MUXCTL_LCSN,
120 MUXCTL_LDC,
121
122 MUXCTL_LSCK,
123 MUXCTL_LSC0,
124 MUXCTL_LSC1,
125 MUXCTL_LHS,
126 MUXCTL_LVS,
127 MUXCTL_LM0,
128 MUXCTL_LM1,
129 MUXCTL_LVP0,
130
131 /* 80: APB_MISC_PP_PIN_MUX_CTL_F_0 */
132 MUXCTL_LD0,
133 MUXCTL_LD1,
134 MUXCTL_LD2,
135 MUXCTL_LD3,
136 MUXCTL_LD4,
137 MUXCTL_LD5,
138 MUXCTL_LD6,
139 MUXCTL_LD7,
140
141 MUXCTL_LD8,
142 MUXCTL_LD9,
143 MUXCTL_LD10,
144 MUXCTL_LD11,
145 MUXCTL_LD12,
146 MUXCTL_LD13,
147 MUXCTL_LD14,
148 MUXCTL_LD15,
149
150 /* 96: APB_MISC_PP_PIN_MUX_CTL_G_0 */
151 MUXCTL_LD16,
152 MUXCTL_LD17,
153 MUXCTL_LHP1,
154 MUXCTL_LHP2,
155 MUXCTL_LVP1,
156 MUXCTL_LHP0,
157 MUXCTL_RESERVED102,
158 MUXCTL_LPP,
159
160 MUXCTL_LDI,
161 MUXCTL_PMC,
162 MUXCTL_CRTP,
163 MUXCTL_PTA,
164 MUXCTL_RESERVED108,
165 MUXCTL_KBCD,
166 MUXCTL_GPU7,
167 MUXCTL_DTF,
168
169 MUXCTL_NONE = -1,
170};
171
172/*
173 * And this defines the order of the pullup/pulldown controls which are again
174 * in a different order
175 */
176enum pmux_pullid {
177 /* 0: APB_MISC_PP_PULLUPDOWN_REG_A_0 */
178 PUCTL_ATA,
179 PUCTL_ATB,
180 PUCTL_ATC,
181 PUCTL_ATD,
182 PUCTL_ATE,
183 PUCTL_DAP1,
184 PUCTL_DAP2,
185 PUCTL_DAP3,
186
187 PUCTL_DAP4,
188 PUCTL_DTA,
189 PUCTL_DTB,
190 PUCTL_DTC,
191 PUCTL_DTD,
192 PUCTL_DTE,
193 PUCTL_DTF,
194 PUCTL_GPV,
195
196 /* 16: APB_MISC_PP_PULLUPDOWN_REG_B_0 */
197 PUCTL_RM,
198 PUCTL_I2CP,
199 PUCTL_PTA,
200 PUCTL_GPU7,
201 PUCTL_KBCA,
202 PUCTL_KBCB,
203 PUCTL_KBCC,
204 PUCTL_KBCD,
205
206 PUCTL_SPDI,
207 PUCTL_SPDO,
208 PUCTL_GPSLXAU,
209 PUCTL_CRTP,
210 PUCTL_SLXC,
211 PUCTL_SLXD,
212 PUCTL_SLXK,
213
214 /* 32: APB_MISC_PP_PULLUPDOWN_REG_C_0 */
215 PUCTL_CDEV1,
216 PUCTL_CDEV2,
217 PUCTL_SPIA,
218 PUCTL_SPIB,
219 PUCTL_SPIC,
220 PUCTL_SPID,
221 PUCTL_SPIE,
222 PUCTL_SPIF,
223
224 PUCTL_SPIG,
225 PUCTL_SPIH,
226 PUCTL_IRTX,
227 PUCTL_IRRX,
228 PUCTL_GME,
229 PUCTL_RESERVED45,
230 PUCTL_XM2D,
231 PUCTL_XM2C,
232
233 /* 48: APB_MISC_PP_PULLUPDOWN_REG_D_0 */
234 PUCTL_UAA,
235 PUCTL_UAB,
236 PUCTL_UAC,
237 PUCTL_UAD,
238 PUCTL_UCA,
239 PUCTL_UCB,
240 PUCTL_LD17,
241 PUCTL_LD19_18,
242
243 PUCTL_LD21_20,
244 PUCTL_LD23_22,
245 PUCTL_LS,
246 PUCTL_LC,
247 PUCTL_CSUS,
248 PUCTL_DDRC,
249 PUCTL_SDC,
250 PUCTL_SDD,
251
252 /* 64: APB_MISC_PP_PULLUPDOWN_REG_E_0 */
253 PUCTL_KBCF,
254 PUCTL_KBCE,
255 PUCTL_PMCA,
256 PUCTL_PMCB,
257 PUCTL_PMCC,
258 PUCTL_PMCD,
259 PUCTL_PMCE,
260 PUCTL_CK32,
261
262 PUCTL_UDA,
263 PUCTL_SDMMC1,
264 PUCTL_GMA,
265 PUCTL_GMB,
266 PUCTL_GMC,
267 PUCTL_GMD,
268 PUCTL_DDC,
269 PUCTL_OWC,
270
271 PUCTL_NONE = -1
272};
273
274struct tegra_pingroup_desc {
275 const char *name;
276 enum pmux_func funcs[4];
277 enum pmux_func func_safe;
278 enum pmux_vddio vddio;
279 enum pmux_ctlid ctl_id;
280 enum pmux_pullid pull_id;
281};
282
283
284/* Converts a pmux_pingrp number to a tristate register: 0=A, 1=B, 2=C, 3=D */
285#define TRISTATE_REG(pmux_pingrp) ((pmux_pingrp) >> 5)
286
287/* Mask value for a tristate (within TRISTATE_REG(id)) */
288#define TRISTATE_MASK(pmux_pingrp) (1 << ((pmux_pingrp) & 0x1f))
289
290/* Converts a PUCTL id to a pull register: 0=A, 1=B...4=E */
291#define PULL_REG(pmux_pullid) ((pmux_pullid) >> 4)
292
293/* Converts a PUCTL id to a shift position */
294#define PULL_SHIFT(pmux_pullid) ((pmux_pullid << 1) & 0x1f)
295
296/* Converts a MUXCTL id to a ctl register: 0=A, 1=B...6=G */
297#define MUXCTL_REG(pmux_ctlid) ((pmux_ctlid) >> 4)
298
299/* Converts a MUXCTL id to a shift position */
300#define MUXCTL_SHIFT(pmux_ctlid) ((pmux_ctlid << 1) & 0x1f)
301
302/* Convenient macro for defining pin group properties */
303#define PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, mux, pupd) \
304 { \
305 .vddio = PMUX_VDDIO_ ## vdd, \
306 .funcs = { \
307 PMUX_FUNC_ ## f0, \
308 PMUX_FUNC_ ## f1, \
309 PMUX_FUNC_ ## f2, \
310 PMUX_FUNC_ ## f3, \
311 }, \
312 .func_safe = PMUX_FUNC_ ## f_safe, \
313 .ctl_id = mux, \
314 .pull_id = pupd \
315 }
316
317/* A normal pin group where the mux name and pull-up name match */
318#define PIN(pg_name, vdd, f0, f1, f2, f3, f_safe) \
319 PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, \
320 MUXCTL_ ## pg_name, PUCTL_ ## pg_name)
321
322/* A pin group where the pull-up name doesn't have a 1-1 mapping */
323#define PINP(pg_name, vdd, f0, f1, f2, f3, f_safe, pupd) \
324 PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, \
325 MUXCTL_ ## pg_name, PUCTL_ ## pupd)
326
327/* A pin group number which is not used */
328#define PIN_RESERVED \
329 PIN(NONE, NONE, NONE, NONE, NONE, NONE, NONE)
330
331const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
332 PIN(ATA, NAND, IDE, NAND, GMI, RSVD, IDE),
333 PIN(ATB, NAND, IDE, NAND, GMI, SDIO4, IDE),
334 PIN(ATC, NAND, IDE, NAND, GMI, SDIO4, IDE),
335 PIN(ATD, NAND, IDE, NAND, GMI, SDIO4, IDE),
336 PIN(CDEV1, AUDIO, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, OSC),
337 PIN(CDEV2, AUDIO, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, OSC),
338 PIN(CSUS, VI, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK,
339 PLLC_OUT1),
340 PIN(DAP1, AUDIO, DAP1, RSVD, GMI, SDIO2, DAP1),
341
342 PIN(DAP2, AUDIO, DAP2, TWC, RSVD, GMI, DAP2),
343 PIN(DAP3, BB, DAP3, RSVD, RSVD, RSVD, DAP3),
344 PIN(DAP4, UART, DAP4, RSVD, GMI, RSVD, DAP4),
345 PIN(DTA, VI, RSVD, SDIO2, VI, RSVD, RSVD4),
346 PIN(DTB, VI, RSVD, RSVD, VI, SPI1, RSVD1),
347 PIN(DTC, VI, RSVD, RSVD, VI, RSVD, RSVD1),
348 PIN(DTD, VI, RSVD, SDIO2, VI, RSVD, RSVD1),
349 PIN(DTE, VI, RSVD, RSVD, VI, SPI1, RSVD1),
350
351 PINP(GPU, UART, PWM, UARTA, GMI, RSVD, RSVD4,
352 GPSLXAU),
353 PIN(GPV, SD, PCIE, RSVD, RSVD, RSVD, PCIE),
354 PIN(I2CP, SYS, I2C, RSVD, RSVD, RSVD, RSVD4),
355 PIN(IRTX, UART, UARTA, UARTB, GMI, SPI4, UARTB),
356 PIN(IRRX, UART, UARTA, UARTB, GMI, SPI4, UARTB),
357 PIN(KBCB, SYS, KBC, NAND, SDIO2, MIO, KBC),
358 PIN(KBCA, SYS, KBC, NAND, SDIO2, EMC_TEST0_DLL, KBC),
359 PINP(PMC, SYS, PWR_ON, PWR_INTR, RSVD, RSVD, PWR_ON, NONE),
360
361 PIN(PTA, NAND, I2C2, HDMI, GMI, RSVD, RSVD4),
362 PIN(RM, UART, I2C, RSVD, RSVD, RSVD, RSVD4),
363 PIN(KBCE, SYS, KBC, NAND, OWR, RSVD, KBC),
364 PIN(KBCF, SYS, KBC, NAND, TRACE, MIO, KBC),
365 PIN(GMA, NAND, UARTE, SPI3, GMI, SDIO4, SPI3),
366 PIN(GMC, NAND, UARTD, SPI4, GMI, SFLASH, SPI4),
367 PIN(SDMMC1, BB, SDIO1, RSVD, UARTE, UARTA, RSVD2),
368 PIN(OWC, SYS, OWR, RSVD, RSVD, RSVD, OWR),
369
370 PIN(GME, NAND, RSVD, DAP5, GMI, SDIO4, GMI),
371 PIN(SDC, SD, PWM, TWC, SDIO3, SPI3, TWC),
372 PIN(SDD, SD, UARTA, PWM, SDIO3, SPI3, PWM),
373 PIN_RESERVED,
374 PINP(SLXA, SD, PCIE, SPI4, SDIO3, SPI2, PCIE, CRTP),
375 PIN(SLXC, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4),
376 PIN(SLXD, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4),
377 PIN(SLXK, SD, PCIE, SPI4, SDIO3, SPI2, PCIE),
378
379 PIN(SPDI, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2),
380 PIN(SPDO, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2),
381 PIN(SPIA, AUDIO, SPI1, SPI2, SPI3, GMI, GMI),
382 PIN(SPIB, AUDIO, SPI1, SPI2, SPI3, GMI, GMI),
383 PIN(SPIC, AUDIO, SPI1, SPI2, SPI3, GMI, GMI),
384 PIN(SPID, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI),
385 PIN(SPIE, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI),
386 PIN(SPIF, AUDIO, SPI3, SPI1, SPI2, RSVD, RSVD4),
387
388 PIN(SPIG, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT),
389 PIN(SPIH, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT),
390 PIN(UAA, BB, SPI3, MIPI_HS, UARTA, ULPI, MIPI_HS),
391 PIN(UAB, BB, SPI2, MIPI_HS, UARTA, ULPI, MIPI_HS),
392 PIN(UAC, BB, OWR, RSVD, RSVD, RSVD, RSVD4),
393 PIN(UAD, UART, IRDA, SPDIF, UARTA, SPI4, SPDIF),
394 PIN(UCA, UART, UARTC, RSVD, GMI, RSVD, RSVD4),
395 PIN(UCB, UART, UARTC, PWM, GMI, RSVD, RSVD4),
396
397 PIN_RESERVED,
398 PIN(ATE, NAND, IDE, NAND, GMI, RSVD, IDE),
399 PIN(KBCC, SYS, KBC, NAND, TRACE, EMC_TEST1_DLL, KBC),
400 PIN_RESERVED,
401 PIN_RESERVED,
402 PIN(GMB, NAND, IDE, NAND, GMI, GMI_INT, GMI),
403 PIN(GMD, NAND, RSVD, NAND, GMI, SFLASH, GMI),
404 PIN(DDC, LCD, I2C2, RSVD, RSVD, RSVD, RSVD4),
405
406 /* 64 */
407 PINP(LD0, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
408 PINP(LD1, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
409 PINP(LD2, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
410 PINP(LD3, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
411 PINP(LD4, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
412 PINP(LD5, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
413 PINP(LD6, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
414 PINP(LD7, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
415
416 PINP(LD8, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
417 PINP(LD9, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
418 PINP(LD10, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
419 PINP(LD11, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
420 PINP(LD12, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
421 PINP(LD13, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
422 PINP(LD14, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
423 PINP(LD15, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
424
425 PINP(LD16, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
426 PINP(LD17, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD17),
427 PINP(LHP0, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD21_20),
428 PINP(LHP1, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD19_18),
429 PINP(LHP2, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD19_18),
430 PINP(LVP0, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LC),
431 PINP(LVP1, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD21_20),
432 PINP(HDINT, LCD, HDMI, RSVD, RSVD, RSVD, HDMI , LC),
433
434 PINP(LM0, LCD, DISPA, DISPB, SPI3, RSVD, RSVD4, LC),
435 PINP(LM1, LCD, DISPA, DISPB, RSVD, CRT, RSVD3, LC),
436 PINP(LVS, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LC),
437 PINP(LSC0, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LC),
438 PINP(LSC1, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
439 PINP(LSCK, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
440 PINP(LDC, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LS),
441 PINP(LCSN, LCD, DISPA, DISPB, SPI3, RSVD, RSVD4, LS),
442
443 /* 96 */
444 PINP(LSPI, LCD, DISPA, DISPB, XIO, HDMI, DISPA, LC),
445 PINP(LSDA, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
446 PINP(LSDI, LCD, DISPA, DISPB, SPI3, RSVD, DISPA, LS),
447 PINP(LPW0, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
448 PINP(LPW1, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LS),
449 PINP(LPW2, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
450 PINP(LDI, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD23_22),
451 PINP(LHS, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LC),
452
453 PINP(LPP, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD23_22),
454 PIN_RESERVED,
455 PIN(KBCD, SYS, KBC, NAND, SDIO2, MIO, KBC),
456 PIN(GPU7, SYS, RTCK, RSVD, RSVD, RSVD, RTCK),
457 PIN(DTF, VI, I2C3, RSVD, VI, RSVD, RSVD4),
458 PIN(UDA, BB, SPI1, RSVD, UARTD, ULPI, RSVD2),
459 PIN(CRTP, LCD, CRT, RSVD, RSVD, RSVD, RSVD),
460 PINP(SDB, SD, UARTA, PWM, SDIO3, SPI2, PWM, NONE),
461
462 /* these pin groups only have pullup and pull down control */
463 PINALL(CK32, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
464 PUCTL_NONE),
465 PINALL(DDRC, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
466 PUCTL_NONE),
467 PINALL(PMCA, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
468 PUCTL_NONE),
469 PINALL(PMCB, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
470 PUCTL_NONE),
471 PINALL(PMCC, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
472 PUCTL_NONE),
473 PINALL(PMCD, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
474 PUCTL_NONE),
475 PINALL(PMCE, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
476 PUCTL_NONE),
477 PINALL(XM2C, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
478 PUCTL_NONE),
479 PINALL(XM2D, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
480 PUCTL_NONE),
481};
482
Simon Glassc3cf49d2011-09-21 12:40:05 +0000[diff] [blame]483void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
Simon Glass858bd092011-08-30 06:23:14 +0000[diff] [blame]484{
Simon Glass20e18e02011-09-21 12:40:06 +0000[diff] [blame]485 struct pmux_tri_ctlr *pmt =
486 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
Simon Glass858bd092011-08-30 06:23:14 +0000[diff] [blame]487 u32 *tri = &pmt->pmt_tri[TRISTATE_REG(pin)];
488 u32 reg;
489
490 reg = readl(tri);
491 if (enable)
492 reg |= TRISTATE_MASK(pin);
493 else
494 reg &= ~TRISTATE_MASK(pin);
495 writel(reg, tri);
496}
497
Simon Glassc3cf49d2011-09-21 12:40:05 +0000[diff] [blame]498void pinmux_tristate_enable(enum pmux_pingrp pin)
Simon Glass858bd092011-08-30 06:23:14 +0000[diff] [blame]499{
500 pinmux_set_tristate(pin, 1);
501}
502
Simon Glassc3cf49d2011-09-21 12:40:05 +0000[diff] [blame]503void pinmux_tristate_disable(enum pmux_pingrp pin)
Simon Glass858bd092011-08-30 06:23:14 +0000[diff] [blame]504{
505 pinmux_set_tristate(pin, 0);
506}
Simon Glass20e18e02011-09-21 12:40:06 +0000[diff] [blame]507
508void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
509{
510 struct pmux_tri_ctlr *pmt =
511 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
512 enum pmux_pullid pull_id = tegra_soc_pingroups[pin].pull_id;
513 u32 *pull = &pmt->pmt_pull[PULL_REG(pull_id)];
514 u32 mask_bit;
515 u32 reg;
516 mask_bit = PULL_SHIFT(pull_id);
517
518 reg = readl(pull);
519 reg &= ~(0x3 << mask_bit);
520 reg |= pupd << mask_bit;
521 writel(reg, pull);
522}
523
524void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
525{
526 struct pmux_tri_ctlr *pmt =
527 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
528 enum pmux_ctlid mux_id = tegra_soc_pingroups[pin].ctl_id;
529 u32 *muxctl = &pmt->pmt_ctl[MUXCTL_REG(mux_id)];
530 u32 mask_bit;
531 int i, mux = -1;
532 u32 reg;
533
534 assert(pmux_func_isvalid(func));
535
536 /* Handle special values */
537 if (func >= PMUX_FUNC_RSVD1) {
538 mux = (func - PMUX_FUNC_RSVD1) & 0x3;
539 } else {
540 /* Search for the appropriate function */
541 for (i = 0; i < 4; i++) {
542 if (tegra_soc_pingroups[pin].funcs[i] == func) {
543 mux = i;
544 break;
545 }
546 }
547 }
548 assert(mux != -1);
549
550 mask_bit = MUXCTL_SHIFT(mux_id);
551 reg = readl(muxctl);
552 reg &= ~(0x3 << mask_bit);
553 reg |= mux << mask_bit;
554 writel(reg, muxctl);
555}
556
557void pinmux_config_pingroup(struct pingroup_config *config)
558{
559 enum pmux_pingrp pin = config->pingroup;
560
561 pinmux_set_func(pin, config->func);
562 pinmux_set_pullupdown(pin, config->pull);
563 pinmux_set_tristate(pin, config->tristate);
564}
565
566void pinmux_config_table(struct pingroup_config *config, int len)
567{
568 int i;
569
570 for (i = 0; i < len; i++)
571 pinmux_config_pingroup(&config[i]);
572}