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Sergey Kubushync74b2102007-08-10 20:26:18 +02001/*
2 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
3 *
4 * Parts shamelesly stolen from Linux Kernel source tree.
5 *
6 * ------------------------------------------------------------
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26#ifndef _NAND_DEFS_H_
27#define _NAND_DEFS_H_
28
29#include <asm/arch/hardware.h>
30
31#define MASK_CLE 0x10
32#define MASK_ALE 0x0a
33
34#define NAND_CE0CLE ((volatile u_int8_t *)(CFG_NAND_BASE + 0x10))
35#define NAND_CE0ALE ((volatile u_int8_t *)(CFG_NAND_BASE + 0x0a))
36#define NAND_CE0DATA ((volatile u_int8_t *)CFG_NAND_BASE)
37
38typedef struct {
39 u_int32_t NRCSR;
40 u_int32_t AWCCR;
41 u_int8_t RSVD0[8];
42 u_int32_t AB1CR;
43 u_int32_t AB2CR;
44 u_int32_t AB3CR;
45 u_int32_t AB4CR;
46 u_int8_t RSVD1[32];
47 u_int32_t NIRR;
48 u_int32_t NIMR;
49 u_int32_t NIMSR;
50 u_int32_t NIMCR;
51 u_int8_t RSVD2[16];
52 u_int32_t NANDFCR;
53 u_int32_t NANDFSR;
54 u_int8_t RSVD3[8];
55 u_int32_t NANDF1ECC;
56 u_int32_t NANDF2ECC;
57 u_int32_t NANDF3ECC;
58 u_int32_t NANDF4ECC;
59 u_int8_t RSVD4[4];
60 u_int32_t IODFTECR;
61 u_int32_t IODFTGCR;
62 u_int8_t RSVD5[4];
63 u_int32_t IODFTMRLR;
64 u_int32_t IODFTMRMR;
65 u_int32_t IODFTMRMSBR;
66 u_int8_t RSVD6[20];
67 u_int32_t MODRNR;
68 u_int8_t RSVD7[76];
69 u_int32_t CE0DATA;
70 u_int32_t CE0ALE;
71 u_int32_t CE0CLE;
72 u_int8_t RSVD8[4];
73 u_int32_t CE1DATA;
74 u_int32_t CE1ALE;
75 u_int32_t CE1CLE;
76 u_int8_t RSVD9[4];
77 u_int32_t CE2DATA;
78 u_int32_t CE2ALE;
79 u_int32_t CE2CLE;
80 u_int8_t RSVD10[4];
81 u_int32_t CE3DATA;
82 u_int32_t CE3ALE;
83 u_int32_t CE3CLE;
84} nand_registers;
85
86typedef volatile nand_registers *nandregs;
87
88#define NAND_READ_START 0x00
89#define NAND_READ_END 0x30
90#define NAND_STATUS 0x70
91
92#ifdef CFG_NAND_HW_ECC
93#define NAND_Ecc_P1e (1 << 0)
94#define NAND_Ecc_P2e (1 << 1)
95#define NAND_Ecc_P4e (1 << 2)
96#define NAND_Ecc_P8e (1 << 3)
97#define NAND_Ecc_P16e (1 << 4)
98#define NAND_Ecc_P32e (1 << 5)
99#define NAND_Ecc_P64e (1 << 6)
100#define NAND_Ecc_P128e (1 << 7)
101#define NAND_Ecc_P256e (1 << 8)
102#define NAND_Ecc_P512e (1 << 9)
103#define NAND_Ecc_P1024e (1 << 10)
104#define NAND_Ecc_P2048e (1 << 11)
105
106#define NAND_Ecc_P1o (1 << 16)
107#define NAND_Ecc_P2o (1 << 17)
108#define NAND_Ecc_P4o (1 << 18)
109#define NAND_Ecc_P8o (1 << 19)
110#define NAND_Ecc_P16o (1 << 20)
111#define NAND_Ecc_P32o (1 << 21)
112#define NAND_Ecc_P64o (1 << 22)
113#define NAND_Ecc_P128o (1 << 23)
114#define NAND_Ecc_P256o (1 << 24)
115#define NAND_Ecc_P512o (1 << 25)
116#define NAND_Ecc_P1024o (1 << 26)
117#define NAND_Ecc_P2048o (1 << 27)
118
119#define TF(v) (v ? 1 : 0)
120
121#define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0)
122#define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1)
123#define P1e(a) (TF(a & NAND_Ecc_P1e) << 2)
124#define P1o(a) (TF(a & NAND_Ecc_P1o) << 3)
125#define P2e(a) (TF(a & NAND_Ecc_P2e) << 4)
126#define P2o(a) (TF(a & NAND_Ecc_P2o) << 5)
127#define P4e(a) (TF(a & NAND_Ecc_P4e) << 6)
128#define P4o(a) (TF(a & NAND_Ecc_P4o) << 7)
129
130#define P8e(a) (TF(a & NAND_Ecc_P8e) << 0)
131#define P8o(a) (TF(a & NAND_Ecc_P8o) << 1)
132#define P16e(a) (TF(a & NAND_Ecc_P16e) << 2)
133#define P16o(a) (TF(a & NAND_Ecc_P16o) << 3)
134#define P32e(a) (TF(a & NAND_Ecc_P32e) << 4)
135#define P32o(a) (TF(a & NAND_Ecc_P32o) << 5)
136#define P64e(a) (TF(a & NAND_Ecc_P64e) << 6)
137#define P64o(a) (TF(a & NAND_Ecc_P64o) << 7)
138
139#define P128e(a) (TF(a & NAND_Ecc_P128e) << 0)
140#define P128o(a) (TF(a & NAND_Ecc_P128o) << 1)
141#define P256e(a) (TF(a & NAND_Ecc_P256e) << 2)
142#define P256o(a) (TF(a & NAND_Ecc_P256o) << 3)
143#define P512e(a) (TF(a & NAND_Ecc_P512e) << 4)
144#define P512o(a) (TF(a & NAND_Ecc_P512o) << 5)
145#define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6)
146#define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7)
147
148#define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0)
149#define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1)
150#define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2)
151#define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3)
152#define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4)
153#define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5)
154#define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6)
155#define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7)
156
157#define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0)
158#define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1)
159#endif
160
161#endif