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Sergei Poselenov5d108ac2008-04-30 11:42:50 +02001/*
2 * (C) Copyright 2008
3 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
4 *
5 * Copyright 2008 Freescale Semiconductor, Inc.
6 *
7 * (C) Copyright 2000
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29#include <common.h>
30#include <asm/mmu.h>
31
32struct fsl_e_tlb_entry tlb_table[] = {
33 /* TLB 0 - for temp stack in cache */
34 SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
35 MAS3_SX|MAS3_SW|MAS3_SR, 0,
36 0, 0, BOOKE_PAGESZ_4K, 0),
37 SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
38 MAS3_SX|MAS3_SW|MAS3_SR, 0,
39 0, 0, BOOKE_PAGESZ_4K, 0),
40 SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
41 MAS3_SX|MAS3_SW|MAS3_SR, 0,
42 0, 0, BOOKE_PAGESZ_4K, 0),
43 SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
44 MAS3_SX|MAS3_SW|MAS3_SR, 0,
45 0, 0, BOOKE_PAGESZ_4K, 0),
46
47
48 /*
Sergei Poselenov59abd152008-06-06 15:42:41 +020049 * TLB 0: 64M Non-cacheable, guarded
50 * 0xfc000000 64M FLASH
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020051 * Out of reset this entry is only 4K.
52 */
53 SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
54 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
55 0, 1, BOOKE_PAGESZ_64M, 1),
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020056
57 /*
58 * TLB 2: 256M Non-cacheable, guarded
59 * 0x80000000 256M PCI1 MEM First half
60 */
61 SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
62 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
63 0, 2, BOOKE_PAGESZ_256M, 1),
64
65 /*
66 * TLB 3: 256M Non-cacheable, guarded
67 * 0x90000000 256M PCI1 MEM Second half
68 */
69 SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000,
70 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
71 0, 3, BOOKE_PAGESZ_256M, 1),
72
Sergei Poselenov59abd152008-06-06 15:42:41 +020073#if defined(CFG_FPGA_BASE)
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020074 /*
Sergei Poselenov59abd152008-06-06 15:42:41 +020075 * TLB 4: 1M Non-cacheable, guarded
76 * 0xc0000000 1M FPGA and NAND
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020077 */
Sergei Poselenov59abd152008-06-06 15:42:41 +020078 SET_TLB_ENTRY(1, CFG_FPGA_BASE, CFG_FPGA_BASE,
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020079 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
Sergei Poselenov59abd152008-06-06 15:42:41 +020080 0, 4, BOOKE_PAGESZ_1M, 1),
81#endif
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020082
83 /*
84 * TLB 6: 64M Non-cacheable, guarded
85 * 0xe000_0000 1M CCSRBAR
86 * 0xe200_0000 16M PCI1 IO
87 */
88 SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
89 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
90 0, 6, BOOKE_PAGESZ_64M, 1),
91
92 /*
93 * TLB 7+8: 512M DDR, cache disabled (needed for memory test)
94 * 0x00000000 512M DDR System memory
95 * Without SPD EEPROM configured DDR, this must be setup manually.
96 * Make sure the TLB count at the top of this table is correct.
97 * Likely it needs to be increased by two for these entries.
98 */
99 SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
100 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
101 0, 7, BOOKE_PAGESZ_256M, 1),
102
103 SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x10000000, CFG_DDR_SDRAM_BASE + 0x10000000,
104 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
105 0, 8, BOOKE_PAGESZ_256M, 1),
106};
107
108int num_tlb_entries = ARRAY_SIZE(tlb_table);