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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 8a414c4258aeeab93fb83fad0544894597c8bd35 / . / doc / README.mpc7448hpc2
blob: 8659e83673b1852388d6b2ec84d3d88d5969d7f2 [file] [log] [blame]
roy zang69366bf2006-11-02 18:34:47 +0800[diff] [blame]1Freescale MPC7448hpc2 (Taiga) board
2===================================
3
4Created 08/11/2006 Roy Zang
5--------------------------
roy zangee311212006-12-01 11:47:36 +0800[diff] [blame]6MPC7448hpc2 (Taiga) board is a high-performance PowerPC server reference
7design, which is optimized for high speed throughput between the processor and
roy zang69366bf2006-11-02 18:34:47 +0800[diff] [blame]8the memory, disk drive and Ethernet port subsystems.
9
roy zangee311212006-12-01 11:47:36 +0800[diff] [blame]10MPC7448hpc2(Taiga) is designed to the micro-ATX chassis, allowing it to be
11used in 1U or 2U rack-mount chassis¡¯, as well as in standard ATX/Micro-ATX
roy zang69366bf2006-11-02 18:34:47 +0800[diff] [blame]12chassis.
13
14Building U-Boot
15------------------
16The mpc7448hpc2 code base is known to compile using:
roy zangee311212006-12-01 11:47:36 +0800[diff] [blame]17 Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3
roy zang69366bf2006-11-02 18:34:47 +0800[diff] [blame]18
roy zangee311212006-12-01 11:47:36 +0800[diff] [blame]19 $ make mpc7448hpc2_config
20 Configuring for mpc7448hpc2 board...
roy zang69366bf2006-11-02 18:34:47 +0800[diff] [blame]21
roy zangee311212006-12-01 11:47:36 +0800[diff] [blame]22 $ make
roy zang69366bf2006-11-02 18:34:47 +0800[diff] [blame]23
24Memory Map
25----------
26
27The memory map is setup for Linux to operate properly.
28
29The mapping is:
30
roy zangee311212006-12-01 11:47:36 +0800[diff] [blame]31 Range Start Range End Definition Size
roy zang69366bf2006-11-02 18:34:47 +0800[diff] [blame]32
roy zangee311212006-12-01 11:47:36 +0800[diff] [blame]33 0x0000_0000 0x7fff_ffff DDR 2G
34 0xe000_0000 0xe7ff_ffff PCI Memory 128M
35 0xfa00_0000 0xfaff_ffff PCI IO 16M
36 0xfb00_0000 0xfbff_ffff PCI Config 16M
37 0xfc00_0000 0xfc0f_ffff NVRAM/CADMUS 1M
38 0xfe00_0000 0xfeff_ffff PromJet 16M
39 0xff00_0000 0xff80_0000 FLASH (boot flash) 8M
40 0xff80_0000 0xffff_ffff FLASH (second half flash) 8M
roy zang69366bf2006-11-02 18:34:47 +0800[diff] [blame]41
42Using Flash
43-----------
44
roy zangee311212006-12-01 11:47:36 +0800[diff] [blame]45The MPC7448hpc2 board has two "banks" of flash, each 8MB in size
46(2^23 = 0x00800000).
roy zang69366bf2006-11-02 18:34:47 +0800[diff] [blame]47
roy zangee311212006-12-01 11:47:36 +0800[diff] [blame]48Note: the "bank" here refers to half of the flash. In fact, there is only one
roy zang69366bf2006-11-02 18:34:47 +0800[diff] [blame]49bank of flash, which is divided into low and high half. Each is controlled by
50the most significant bit of the address bus. The so called "bank" is only for
51convenience.
52
53There is a switch which allows the "bank" to be selected. The switch
54settings for updating flash are given below.
55
56The u-boot commands for copying the boot-bank into the secondary bank are
57as follows:
58
roy zangee311212006-12-01 11:47:36 +0800[diff] [blame]59 erase ff800000 ff880000
60 cp.b ff000000 ff800000 80000
roy zang69366bf2006-11-02 18:34:47 +0800[diff] [blame]61
62U-boot commands for downloading an image via tftp and flashing
63it into the secondary bank:
64
roy zangee311212006-12-01 11:47:36 +0800[diff] [blame]65 tftp 10000 <u-boot.bin.image>
66 erase ff000000 ff080000
67 cp.b 10000 ff000000 80000
roy zang69366bf2006-11-02 18:34:47 +0800[diff] [blame]68
69After copying the image into the second bank of flash, be sure to toggle
70SW3[4] on board before resetting the board in order to set the
71secondary bank as the boot-bank.
72
roy zang69366bf2006-11-02 18:34:47 +0800[diff] [blame]73Board Switches
74----------------------
75
roy zang69366bf2006-11-02 18:34:47 +0800[diff] [blame]76Most switches on the board should not be changed. The most frequent
77user-settable switches on the board are used to configure
78the flash banks and determining the PCI frequency.
79
80SW1[1-5]: Processor core voltage
81
roy zangee311212006-12-01 11:47:36 +0800[diff] [blame]82 12345 Core Voltage
83 -----
84 SW1=01111 1.000V.
85 SW1=01101 1.100V.
86 SW1=01011 1.200V.
87 SW1=01001 1.300V only for MPC7447A.
roy zang69366bf2006-11-02 18:34:47 +0800[diff] [blame]88
89
90SW2[1-6]: CPU core frequency
91
roy zangee311212006-12-01 11:47:36 +0800[diff] [blame]92 CPU Core Frequency (MHz)
roy zang69366bf2006-11-02 18:34:47 +0800[diff] [blame]93 Bus Frequency
roy zangee311212006-12-01 11:47:36 +0800[diff] [blame]94 123456 100 133 167 200 Ratio
Wolfgang Denk647d3c32007-03-04 01:36:05 +0100[diff] [blame]95
roy zangee311212006-12-01 11:47:36 +0800[diff] [blame]96 ------
97 SW2=101100 500 667 833 1000 5x
98 SW2=100100 550 733 917 1100 5.5x
99 SW2=110100 600 800 1000 1200 6x
100 SW2=010100 650 866 1083 1300 6.5x
101 SW2=001000 700 930 1167 1400 7x
102 SW2=000100 750 1000 1250 1500 7.5x
103 SW2=110000 800 1066 1333 1600 8x
104 SW2=011000 850 1333 1417 1700 8.5x only for MPC7447A
105 SW2=011110 900 1200 1500 1800 9x
roy zang69366bf2006-11-02 18:34:47 +0800[diff] [blame]106
roy zangee311212006-12-01 11:47:36 +0800[diff] [blame]107This table shows only a subset of available frequency options; see the CPU
roy zang69366bf2006-11-02 18:34:47 +0800[diff] [blame]108hardware specifications for more information.
109
roy zang69366bf2006-11-02 18:34:47 +0800[diff] [blame]110SW2[7-8]: Bus Protocol and CPU Reset Option
111
Wolfgang Denk647d3c32007-03-04 01:36:05 +0100[diff] [blame]112 7
roy zangee311212006-12-01 11:47:36 +0800[diff] [blame]113 -
114 SW2=0 System bus uses MPX bus protocol
115 SW2=1 System bus uses 60x bus protocol
roy zang69366bf2006-11-02 18:34:47 +0800[diff] [blame]116
Wolfgang Denk647d3c32007-03-04 01:36:05 +0100[diff] [blame]117 8
roy zangee311212006-12-01 11:47:36 +0800[diff] [blame]118 -
119 SW2=0 TSI108 can cause CPU reset
120 SW2=1 TSI108 can not cause CPU reset
roy zang69366bf2006-11-02 18:34:47 +0800[diff] [blame]121
122SW3[1-8] system options
123
Wolfgang Denk647d3c32007-03-04 01:36:05 +0100[diff] [blame]124 123
roy zangee311212006-12-01 11:47:36 +0800[diff] [blame]125 ---
126 SW3=xxx Connected to GPIO[0:2] on TSI108
roy zang69366bf2006-11-02 18:34:47 +0800[diff] [blame]127
Wolfgang Denk647d3c32007-03-04 01:36:05 +0100[diff] [blame]128 4
roy zangee311212006-12-01 11:47:36 +0800[diff] [blame]129 -
130 SW3=0 CPU boots from low half of flash
131 SW3=1 CPU boots from high half of flash
roy zang69366bf2006-11-02 18:34:47 +0800[diff] [blame]132
Wolfgang Denk647d3c32007-03-04 01:36:05 +0100[diff] [blame]133 5
roy zangee311212006-12-01 11:47:36 +0800[diff] [blame]134 -
135 SW3=0 SATA and slot2 connected to PCI bus
136 SW3=1 Only slot1 connected to PCI bus
roy zang69366bf2006-11-02 18:34:47 +0800[diff] [blame]137
Wolfgang Denk647d3c32007-03-04 01:36:05 +0100[diff] [blame]138 6
roy zangee311212006-12-01 11:47:36 +0800[diff] [blame]139 -
140 SW3=0 USB connected to PCI bus
141 SW3=1 USB disconnected from PCI bus
roy zang69366bf2006-11-02 18:34:47 +0800[diff] [blame]142
Wolfgang Denk647d3c32007-03-04 01:36:05 +0100[diff] [blame]143 7
roy zangee311212006-12-01 11:47:36 +0800[diff] [blame]144 -
145 SW3=0 Flash is write protected
146 SW3=1 Flash is NOT write protected
roy zang69366bf2006-11-02 18:34:47 +0800[diff] [blame]147
Wolfgang Denk647d3c32007-03-04 01:36:05 +0100[diff] [blame]148 8
roy zangee311212006-12-01 11:47:36 +0800[diff] [blame]149 -
150 SW3=0 CPU will boot from flash
151 SW3=1 CPU will boot from PromJet
roy zang69366bf2006-11-02 18:34:47 +0800[diff] [blame]152
153SW4[1-3]: System bus frequency
154
155 Bus Frequency (MHz)
roy zangee311212006-12-01 11:47:36 +0800[diff] [blame]156 ---
157 SW4=010 183
158 SW4=011 100
159 SW4=100 133
160 SW4=101 166 only for MPC7447A
161 SW4=110 200 only for MPC7448
162 others reserved
roy zang69366bf2006-11-02 18:34:47 +0800[diff] [blame]163
164SW4[4-6]: DDR2 SDRAM frequency
165
166 Bus Frequency (MHz)
roy zangee311212006-12-01 11:47:36 +0800[diff] [blame]167 ---
168 SW4=000 external clock
Wolfgang Denk647d3c32007-03-04 01:36:05 +0100[diff] [blame]169 SW4=011 system clock
roy zangee311212006-12-01 11:47:36 +0800[diff] [blame]170 SW4=100 133
171 SW4=101 166
172 SW4=110 200
173 others reserved
roy zang69366bf2006-11-02 18:34:47 +0800[diff] [blame]174
175SW4[7-8]: PCI/PCI-X frequency control
Wolfgang Denk647d3c32007-03-04 01:36:05 +0100[diff] [blame]176 7
roy zangee311212006-12-01 11:47:36 +0800[diff] [blame]177 -
178 SW4=0 PCI/PCI-X bus operates normally
179 SW4=1 PCI bus forced to PCI-33 mode
roy zang69366bf2006-11-02 18:34:47 +0800[diff] [blame]180
Wolfgang Denk647d3c32007-03-04 01:36:05 +0100[diff] [blame]181 8
roy zangee311212006-12-01 11:47:36 +0800[diff] [blame]182 -
183 SW4=0 PCI-X mode at 133 MHz allowed
184 SW4=1 PCI-X mode limited to 100 MHz