Michal Simek | f22651c | 2012-09-28 09:56:37 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2012 Michal Simek <monstr@monstr.eu> |
| 3 | * |
Wolfgang Denk | 3765b3e | 2013-10-07 13:07:26 +0200 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
Michal Simek | f22651c | 2012-09-28 09:56:37 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <common.h> |
Michal Simek | 9e0e37a | 2014-02-24 11:16:32 +0100 | [diff] [blame] | 8 | #include <fdtdec.h> |
Michal Simek | 5b73caf | 2014-04-25 13:51:17 +0200 | [diff] [blame] | 9 | #include <fpga.h> |
| 10 | #include <mmc.h> |
Michal Simek | d5dae85 | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 11 | #include <zynqpl.h> |
Michal Simek | 7193653 | 2013-04-12 16:33:08 +0200 | [diff] [blame] | 12 | #include <asm/arch/hardware.h> |
| 13 | #include <asm/arch/sys_proto.h> |
Michal Simek | f22651c | 2012-09-28 09:56:37 +0000 | [diff] [blame] | 14 | |
| 15 | DECLARE_GLOBAL_DATA_PTR; |
| 16 | |
Michal Simek | 0b68020 | 2014-03-04 12:41:05 +0100 | [diff] [blame] | 17 | #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ |
| 18 | (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) |
Michal Simek | 5b73caf | 2014-04-25 13:51:17 +0200 | [diff] [blame] | 19 | static xilinx_desc fpga; |
Michal Simek | d5dae85 | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 20 | |
| 21 | /* It can be done differently */ |
Michal Simek | 05c59d0 | 2016-10-18 16:10:25 +0200 | [diff] [blame] | 22 | static xilinx_desc fpga007s = XILINX_XC7Z007S_DESC(0x7); |
Michal Simek | 5b73caf | 2014-04-25 13:51:17 +0200 | [diff] [blame] | 23 | static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); |
Michal Simek | 05c59d0 | 2016-10-18 16:10:25 +0200 | [diff] [blame] | 24 | static xilinx_desc fpga012s = XILINX_XC7Z012S_DESC(0x12); |
| 25 | static xilinx_desc fpga014s = XILINX_XC7Z014S_DESC(0x14); |
Michal Simek | 5b73caf | 2014-04-25 13:51:17 +0200 | [diff] [blame] | 26 | static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15); |
| 27 | static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); |
| 28 | static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); |
Siva Durga Prasad Paladugu | b910380 | 2014-11-25 15:29:54 +0530 | [diff] [blame] | 29 | static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35); |
Michal Simek | 5b73caf | 2014-04-25 13:51:17 +0200 | [diff] [blame] | 30 | static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); |
| 31 | static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100); |
Michal Simek | d5dae85 | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 32 | #endif |
| 33 | |
Michal Simek | f22651c | 2012-09-28 09:56:37 +0000 | [diff] [blame] | 34 | int board_init(void) |
| 35 | { |
Michal Simek | 0b68020 | 2014-03-04 12:41:05 +0100 | [diff] [blame] | 36 | #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ |
| 37 | (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) |
Michal Simek | d5dae85 | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 38 | u32 idcode; |
| 39 | |
| 40 | idcode = zynq_slcr_get_idcode(); |
| 41 | |
| 42 | switch (idcode) { |
Michal Simek | 05c59d0 | 2016-10-18 16:10:25 +0200 | [diff] [blame] | 43 | case XILINX_ZYNQ_7007S: |
| 44 | fpga = fpga007s; |
| 45 | break; |
Michal Simek | d5dae85 | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 46 | case XILINX_ZYNQ_7010: |
| 47 | fpga = fpga010; |
| 48 | break; |
Michal Simek | 05c59d0 | 2016-10-18 16:10:25 +0200 | [diff] [blame] | 49 | case XILINX_ZYNQ_7012S: |
| 50 | fpga = fpga012s; |
| 51 | break; |
| 52 | case XILINX_ZYNQ_7014S: |
| 53 | fpga = fpga014s; |
| 54 | break; |
Michal Simek | 31993d6 | 2013-09-26 16:39:03 +0200 | [diff] [blame] | 55 | case XILINX_ZYNQ_7015: |
| 56 | fpga = fpga015; |
| 57 | break; |
Michal Simek | d5dae85 | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 58 | case XILINX_ZYNQ_7020: |
| 59 | fpga = fpga020; |
| 60 | break; |
| 61 | case XILINX_ZYNQ_7030: |
| 62 | fpga = fpga030; |
| 63 | break; |
Siva Durga Prasad Paladugu | b910380 | 2014-11-25 15:29:54 +0530 | [diff] [blame] | 64 | case XILINX_ZYNQ_7035: |
| 65 | fpga = fpga035; |
| 66 | break; |
Michal Simek | d5dae85 | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 67 | case XILINX_ZYNQ_7045: |
| 68 | fpga = fpga045; |
| 69 | break; |
Michal Simek | fd2b10b | 2013-06-17 13:54:07 +0200 | [diff] [blame] | 70 | case XILINX_ZYNQ_7100: |
| 71 | fpga = fpga100; |
| 72 | break; |
Michal Simek | d5dae85 | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 73 | } |
| 74 | #endif |
| 75 | |
Michal Simek | 0b68020 | 2014-03-04 12:41:05 +0100 | [diff] [blame] | 76 | #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ |
| 77 | (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) |
Michal Simek | d5dae85 | 2013-04-22 15:43:02 +0200 | [diff] [blame] | 78 | fpga_init(); |
| 79 | fpga_add(fpga_xilinx, &fpga); |
| 80 | #endif |
| 81 | |
Michal Simek | f22651c | 2012-09-28 09:56:37 +0000 | [diff] [blame] | 82 | return 0; |
| 83 | } |
| 84 | |
Jagannadha Sutradharudu Teki | b3de924 | 2014-01-09 01:48:21 +0530 | [diff] [blame] | 85 | int board_late_init(void) |
| 86 | { |
| 87 | switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) { |
| 88 | case ZYNQ_BM_NOR: |
| 89 | setenv("modeboot", "norboot"); |
| 90 | break; |
| 91 | case ZYNQ_BM_SD: |
| 92 | setenv("modeboot", "sdboot"); |
| 93 | break; |
| 94 | case ZYNQ_BM_JTAG: |
| 95 | setenv("modeboot", "jtagboot"); |
| 96 | break; |
| 97 | default: |
| 98 | setenv("modeboot", ""); |
| 99 | break; |
| 100 | } |
| 101 | |
| 102 | return 0; |
| 103 | } |
Michal Simek | f22651c | 2012-09-28 09:56:37 +0000 | [diff] [blame] | 104 | |
Michal Simek | 5a82d53 | 2014-08-28 13:31:02 +0200 | [diff] [blame] | 105 | #ifdef CONFIG_DISPLAY_BOARDINFO |
| 106 | int checkboard(void) |
| 107 | { |
Michal Simek | 5af0855 | 2016-01-25 11:04:21 +0100 | [diff] [blame] | 108 | puts("Board: Xilinx Zynq\n"); |
Michal Simek | 5a82d53 | 2014-08-28 13:31:02 +0200 | [diff] [blame] | 109 | return 0; |
| 110 | } |
| 111 | #endif |
| 112 | |
Joe Hershberger | a509a1d | 2016-01-26 11:57:03 -0600 | [diff] [blame] | 113 | int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) |
| 114 | { |
| 115 | #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \ |
| 116 | defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) |
| 117 | if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR, |
| 118 | CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET, |
| 119 | ethaddr, 6)) |
| 120 | printf("I2C EEPROM MAC address read failed\n"); |
| 121 | #endif |
| 122 | |
| 123 | return 0; |
| 124 | } |
| 125 | |
Michal Simek | 758f29d | 2016-04-01 15:56:33 +0200 | [diff] [blame] | 126 | #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE) |
Nathan Rossi | 64b67fb | 2016-12-04 19:33:22 +1000 | [diff] [blame] | 127 | static const void *get_memory_reg_prop(const void *fdt, int *lenp) |
Michal Simek | 758f29d | 2016-04-01 15:56:33 +0200 | [diff] [blame] | 128 | { |
Nathan Rossi | 64b67fb | 2016-12-04 19:33:22 +1000 | [diff] [blame] | 129 | int offset; |
Michal Simek | 758f29d | 2016-04-01 15:56:33 +0200 | [diff] [blame] | 130 | |
Nathan Rossi | 64b67fb | 2016-12-04 19:33:22 +1000 | [diff] [blame] | 131 | offset = fdt_path_offset(fdt, "/memory"); |
| 132 | if (offset < 0) |
| 133 | return NULL; |
Michal Simek | 758f29d | 2016-04-01 15:56:33 +0200 | [diff] [blame] | 134 | |
Nathan Rossi | 64b67fb | 2016-12-04 19:33:22 +1000 | [diff] [blame] | 135 | return fdt_getprop(fdt, offset, "reg", lenp); |
Michal Simek | 758f29d | 2016-04-01 15:56:33 +0200 | [diff] [blame] | 136 | } |
| 137 | |
Michal Simek | 8a5db0a | 2016-12-06 16:31:53 +0100 | [diff] [blame^] | 138 | int dram_init(void) |
| 139 | { |
| 140 | const void *fdt = gd->fdt_blob; |
| 141 | const fdt32_t *val; |
| 142 | int ac, sc, len; |
| 143 | |
| 144 | ac = fdt_address_cells(fdt, 0); |
| 145 | sc = fdt_size_cells(fdt, 0); |
| 146 | if (ac < 0 || sc < 1 || sc > 2) { |
| 147 | printf("invalid address/size cells\n"); |
| 148 | return -EINVAL; |
| 149 | } |
| 150 | |
| 151 | val = get_memory_reg_prop(fdt, &len); |
| 152 | if (len / sizeof(*val) < ac + sc) |
| 153 | return -EINVAL; |
| 154 | |
| 155 | val += ac; |
| 156 | |
| 157 | gd->ram_size = fdtdec_get_number(val, sc); |
| 158 | |
| 159 | debug("DRAM size = %08lx\n", (unsigned long)gd->ram_size); |
| 160 | |
| 161 | zynq_ddrc_init(); |
| 162 | |
| 163 | return 0; |
| 164 | } |
| 165 | |
Michal Simek | 758f29d | 2016-04-01 15:56:33 +0200 | [diff] [blame] | 166 | void dram_init_banksize(void) |
| 167 | { |
Nathan Rossi | 64b67fb | 2016-12-04 19:33:22 +1000 | [diff] [blame] | 168 | const void *fdt = gd->fdt_blob; |
| 169 | const fdt32_t *val; |
| 170 | int ac, sc, cells, len, i; |
Michal Simek | 758f29d | 2016-04-01 15:56:33 +0200 | [diff] [blame] | 171 | |
Nathan Rossi | 64b67fb | 2016-12-04 19:33:22 +1000 | [diff] [blame] | 172 | val = get_memory_reg_prop(fdt, &len); |
| 173 | if (len < 0) |
| 174 | return; |
Michal Simek | 758f29d | 2016-04-01 15:56:33 +0200 | [diff] [blame] | 175 | |
Nathan Rossi | 64b67fb | 2016-12-04 19:33:22 +1000 | [diff] [blame] | 176 | ac = fdt_address_cells(fdt, 0); |
| 177 | sc = fdt_size_cells(fdt, 0); |
| 178 | if (ac < 1 || sc > 2 || sc < 1 || sc > 2) { |
| 179 | printf("invalid address/size cells\n"); |
| 180 | return; |
| 181 | } |
| 182 | |
| 183 | cells = ac + sc; |
| 184 | |
| 185 | len /= sizeof(*val); |
| 186 | |
| 187 | for (i = 0; i < CONFIG_NR_DRAM_BANKS && len >= cells; |
| 188 | i++, len -= cells) { |
| 189 | gd->bd->bi_dram[i].start = fdtdec_get_number(val, ac); |
| 190 | val += ac; |
| 191 | gd->bd->bi_dram[i].size = fdtdec_get_number(val, sc); |
| 192 | val += sc; |
| 193 | |
| 194 | debug("DRAM bank %d: start = %08lx, size = %08lx\n", |
| 195 | i, (unsigned long)gd->bd->bi_dram[i].start, |
| 196 | (unsigned long)gd->bd->bi_dram[i].size); |
Michal Simek | 758f29d | 2016-04-01 15:56:33 +0200 | [diff] [blame] | 197 | } |
| 198 | } |
Michal Simek | 758f29d | 2016-04-01 15:56:33 +0200 | [diff] [blame] | 199 | #else |
| 200 | int dram_init(void) |
| 201 | { |
| 202 | gd->ram_size = CONFIG_SYS_SDRAM_SIZE; |
| 203 | |
| 204 | zynq_ddrc_init(); |
| 205 | |
| 206 | return 0; |
| 207 | } |
| 208 | #endif |