Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 1 | CONFIG_PPC=y |
Tom Rini | 278b90c | 2018-02-03 12:10:38 -0500 | [diff] [blame] | 2 | CONFIG_SYS_TEXT_BASE=0xFE000000 |
Mario Six | ff3bb0c | 2019-01-21 09:17:53 +0100 | [diff] [blame] | 3 | CONFIG_SYS_CLK_FREQ=33333333 |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 4 | CONFIG_MPC83xx=y |
| 5 | CONFIG_TARGET_MPC8308RDB=y |
Mario Six | 21c1502 | 2019-01-21 09:17:54 +0100 | [diff] [blame] | 6 | CONFIG_SYSTEM_PLL_VCO_DIV_2=y |
| 7 | CONFIG_SYSTEM_PLL_FACTOR_4_1=y |
| 8 | CONFIG_CORE_PLL_RATIO_3_1=y |
| 9 | CONFIG_BOOT_MEMORY_SPACE_LOW=y |
| 10 | CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y |
| 11 | CONFIG_TSEC1_MODE_RGMII=y |
| 12 | CONFIG_TSEC2_MODE_RGMII=y |
Mario Six | 30915ab | 2019-01-21 09:17:57 +0100 | [diff] [blame] | 13 | CONFIG_BAT0=y |
| 14 | CONFIG_BAT0_NAME="DDR" |
| 15 | CONFIG_BAT0_BASE=0x00000000 |
| 16 | CONFIG_BAT0_LENGTH_128_MBYTES=y |
| 17 | CONFIG_BAT0_ACCESS_RW=y |
| 18 | CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y |
| 19 | CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y |
| 20 | CONFIG_BAT0_USER_MODE_VALID=y |
| 21 | CONFIG_BAT0_SUPERVISOR_MODE_VALID=y |
| 22 | CONFIG_BAT1=y |
| 23 | CONFIG_BAT1_NAME="IMMRBAR" |
| 24 | CONFIG_BAT1_BASE=0xE0000000 |
| 25 | CONFIG_BAT1_LENGTH_8_MBYTES=y |
| 26 | CONFIG_BAT1_ACCESS_RW=y |
| 27 | CONFIG_BAT1_ICACHE_INHIBITED=y |
| 28 | CONFIG_BAT1_ICACHE_GUARDED=y |
| 29 | CONFIG_BAT1_DCACHE_INHIBITED=y |
| 30 | CONFIG_BAT1_DCACHE_GUARDED=y |
| 31 | CONFIG_BAT1_USER_MODE_VALID=y |
| 32 | CONFIG_BAT1_SUPERVISOR_MODE_VALID=y |
| 33 | CONFIG_BAT2=y |
| 34 | CONFIG_BAT2_NAME="FLASH" |
| 35 | CONFIG_BAT2_BASE=0xFE000000 |
| 36 | CONFIG_BAT2_LENGTH_8_MBYTES=y |
| 37 | CONFIG_BAT2_ACCESS_RW=y |
| 38 | CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y |
| 39 | CONFIG_BAT2_DCACHE_INHIBITED=y |
| 40 | CONFIG_BAT2_DCACHE_GUARDED=y |
| 41 | CONFIG_BAT2_USER_MODE_VALID=y |
| 42 | CONFIG_BAT2_SUPERVISOR_MODE_VALID=y |
| 43 | CONFIG_BAT3=y |
| 44 | CONFIG_BAT3_NAME="STACK_IN_DCACHE" |
| 45 | CONFIG_BAT3_BASE=0xE6000000 |
| 46 | CONFIG_BAT3_ACCESS_RW=y |
| 47 | CONFIG_BAT3_USER_MODE_VALID=y |
| 48 | CONFIG_BAT3_SUPERVISOR_MODE_VALID=y |
Mario Six | 9c5df7a | 2019-01-21 09:17:58 +0100 | [diff] [blame] | 49 | CONFIG_LBLAW0=y |
| 50 | CONFIG_LBLAW0_BASE=0xFE000000 |
| 51 | CONFIG_LBLAW0_NAME="FLASH" |
| 52 | CONFIG_LBLAW0_LENGTH_8_MBYTES=y |
| 53 | CONFIG_LBLAW1=y |
| 54 | CONFIG_LBLAW1_BASE=0xE0600000 |
| 55 | CONFIG_LBLAW1_NAME="NAND" |
| 56 | CONFIG_LBLAW1_LENGTH_32_KBYTES=y |
| 57 | CONFIG_LBLAW2=y |
| 58 | CONFIG_LBLAW2_BASE=0xF0000000 |
| 59 | CONFIG_LBLAW2_NAME="VSC7385" |
| 60 | CONFIG_LBLAW2_LENGTH_128_KBYTES=y |
Mario Six | be5abb0 | 2019-01-21 09:18:09 +0100 | [diff] [blame] | 61 | CONFIG_HID0_FINAL_EMCP=y |
| 62 | CONFIG_HID0_FINAL_DPM=y |
| 63 | CONFIG_HID0_FINAL_ICE=y |
| 64 | CONFIG_HID2_HBE=y |
Mario Six | ba463c1 | 2019-01-21 09:18:11 +0100 | [diff] [blame] | 65 | CONFIG_SICR_ETSEC1_A_TSEC_GTX_CLK125=y |
| 66 | CONFIG_SICR_GPIO_A_TSEC2=y |
| 67 | CONFIG_SICR_GPIO_B_TSEC_GTX_CLK125=y |
| 68 | CONFIG_SICR_IEEE1588_A_GPIO=y |
| 69 | CONFIG_SICR_GTM_GPIO=y |
| 70 | CONFIG_SICR_GPIOSEL_IEEE1588=y |
| 71 | CONFIG_SICR_TMSOBI1_2_5_V=y |
| 72 | CONFIG_SICR_TMSOBI2_2_5_V=y |
Mario Six | 73df96a | 2019-01-21 09:18:12 +0100 | [diff] [blame] | 73 | CONFIG_ACR_PIPE_DEP_4=y |
| 74 | CONFIG_ACR_RPTCNT_4=y |
Mario Six | e35012e | 2019-01-21 09:18:13 +0100 | [diff] [blame] | 75 | CONFIG_SPCR_TSECEP_3=y |
Mario Six | 7c2e535 | 2019-01-21 09:18:14 +0100 | [diff] [blame] | 76 | CONFIG_LCRR_DBYP_PLL_BYPASSED=y |
| 77 | CONFIG_LCRR_CLKDIV_2=y |
Simon Glass | 73223f0 | 2016-02-22 22:55:43 -0700 | [diff] [blame] | 78 | CONFIG_FIT=y |
| 79 | CONFIG_FIT_VERBOSE=y |
| 80 | CONFIG_OF_BOARD_SETUP=y |
| 81 | CONFIG_OF_STDOUT_VIA_ALIAS=y |
Heiko Schocher | bb597c0 | 2016-06-07 08:31:14 +0200 | [diff] [blame] | 82 | CONFIG_BOOTDELAY=5 |
Adam Ford | 8ccf98b | 2018-07-29 13:13:29 -0500 | [diff] [blame] | 83 | CONFIG_MISC_INIT_R=y |
Tom Rini | adad96e | 2016-04-21 21:37:19 -0400 | [diff] [blame] | 84 | CONFIG_HUSH_PARSER=y |
Adam Ford | d021e94 | 2018-02-06 07:58:59 -0600 | [diff] [blame] | 85 | # CONFIG_AUTO_COMPLETE is not set |
Tuomas Tynkkynen | ad12dc1 | 2017-10-08 21:48:01 +0300 | [diff] [blame] | 86 | CONFIG_CMD_IMLS=y |
Tom Rini | 78d1e1d | 2016-04-22 16:41:25 -0400 | [diff] [blame] | 87 | CONFIG_CMD_I2C=y |
Tom Rini | 8866312 | 2017-08-14 19:58:53 -0400 | [diff] [blame] | 88 | CONFIG_CMD_MMC=y |
Simon Glass | 6500ec7 | 2017-08-04 16:34:34 -0600 | [diff] [blame] | 89 | CONFIG_CMD_PCI=y |
Joe Hershberger | ef0f2f5 | 2015-06-22 16:15:30 -0500 | [diff] [blame] | 90 | # CONFIG_CMD_SETEXPR is not set |
Tom Rini | 78d1e1d | 2016-04-22 16:41:25 -0400 | [diff] [blame] | 91 | CONFIG_CMD_DHCP=y |
Tom Rini | 89cb2b5 | 2016-04-24 17:29:26 -0400 | [diff] [blame] | 92 | CONFIG_CMD_MII=y |
Tom Rini | 78d1e1d | 2016-04-22 16:41:25 -0400 | [diff] [blame] | 93 | CONFIG_CMD_PING=y |
Chris Packham | c9032ce | 2017-04-29 15:20:28 +1200 | [diff] [blame] | 94 | CONFIG_CMD_DATE=y |
Tom Rini | 89cb2b5 | 2016-04-24 17:29:26 -0400 | [diff] [blame] | 95 | CONFIG_CMD_FAT=y |
Mario Six | 07dea2e | 2018-03-28 14:38:19 +0200 | [diff] [blame] | 96 | CONFIG_FSL_ESDHC=y |
Masahiro Yamada | e856bdc | 2017-02-11 22:43:54 +0900 | [diff] [blame] | 97 | CONFIG_MTD_NOR_FLASH=y |
Adam Ford | 2fe88d4 | 2018-10-14 15:10:50 -0500 | [diff] [blame] | 98 | CONFIG_FLASH_CFI_DRIVER=y |
| 99 | CONFIG_SYS_FLASH_PROTECTION=y |
| 100 | CONFIG_SYS_FLASH_CFI=y |
Mario Six | a8ca5c8 | 2018-04-27 14:52:21 +0200 | [diff] [blame] | 101 | CONFIG_PHY_MARVELL=y |
Adam Ford | d7869b2 | 2018-07-20 23:03:57 -0500 | [diff] [blame] | 102 | CONFIG_MII=y |
Mario Six | 1715105 | 2018-03-28 14:38:18 +0200 | [diff] [blame] | 103 | CONFIG_TSEC_ENET=y |
Thomas Chou | 9e39003 | 2015-11-19 21:48:14 +0800 | [diff] [blame] | 104 | CONFIG_SYS_NS16550=y |
Simon Glass | 69e173e | 2016-02-22 22:55:42 -0700 | [diff] [blame] | 105 | CONFIG_OF_LIBFDT=y |
Mario Six | fe7d654 | 2019-01-21 09:18:03 +0100 | [diff] [blame] | 106 | CONFIG_ELBC_BR0_OR0=y |
| 107 | CONFIG_BR0_OR0_NAME="FLASH" |
| 108 | CONFIG_BR0_OR0_BASE=0xFE000000 |
| 109 | CONFIG_BR0_MACHINE_GPCM=y |
| 110 | CONFIG_BR0_PORTSIZE_16BIT=y |
| 111 | CONFIG_OR0_AM_8_MBYTES=y |
| 112 | CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y |
| 113 | CONFIG_OR0_CSNT_EARLIER=y |
| 114 | CONFIG_OR0_SCY_15=y |
| 115 | CONFIG_OR0_XACS_EXTENDED=y |
| 116 | CONFIG_OR0_XAM_SET=y |
| 117 | CONFIG_OR0_TRLX_RELAXED=y |
| 118 | CONFIG_OR0_EHTR_8_CYCLE=y |
| 119 | CONFIG_ELBC_BR1_OR1=y |
| 120 | CONFIG_BR1_OR1_NAME="NAND" |
| 121 | CONFIG_BR1_OR1_BASE=0xE0600000 |
| 122 | CONFIG_BR1_ERRORCHECKING_BOTH=y |
| 123 | CONFIG_BR1_MACHINE_FCM=y |
| 124 | CONFIG_BR1_PORTSIZE_8BIT=y |
| 125 | CONFIG_OR1_AM_32_KBYTES=y |
| 126 | CONFIG_OR1_SCY_1=y |
| 127 | CONFIG_OR1_TRLX_RELAXED=y |
| 128 | CONFIG_OR1_CHT_TWO_CLOCK=y |
| 129 | CONFIG_OR1_CSCT_8_CYCLE=y |
| 130 | CONFIG_OR1_CST_ONE_CLOCK=y |
| 131 | CONFIG_OR1_EHTR_8_CYCLE=y |
| 132 | CONFIG_ELBC_BR2_OR2=y |
| 133 | CONFIG_BR2_OR2_NAME="VSC7385_BASE" |
| 134 | CONFIG_BR2_OR2_BASE=0xF0000000 |
| 135 | CONFIG_BR2_MACHINE_GPCM=y |
| 136 | CONFIG_BR2_PORTSIZE_8BIT=y |
| 137 | CONFIG_OR2_AM_128_KBYTES=y |
| 138 | CONFIG_OR2_CSNT_EARLIER=y |
| 139 | CONFIG_OR2_SCY_15=y |
| 140 | CONFIG_OR2_SETA_EXTERNAL=y |
| 141 | CONFIG_OR2_XACS_EXTENDED=y |
| 142 | CONFIG_OR2_TRLX_RELAXED=y |
| 143 | CONFIG_OR2_EHTR_8_CYCLE=y |