blob: b518c222d4365491be6413fb3ab03bcc8625eaab [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -04002/*
3 * Copyright 2013-2015 Arcturus Networks, Inc.
4 * http://www.arcturusnetworks.com/products/ucp1020/
5 * based on include/configs/p1_p2_rdb_pc.h
6 * original copyright follows:
7 * Copyright 2009-2011 Freescale Semiconductor, Inc.
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -04008 */
9
10/*
11 * QorIQ uCP1020-xx boards configuration file
12 */
13#ifndef __CONFIG_H
14#define __CONFIG_H
15
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -040016#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
17#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
18#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
19#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
20#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
21#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
22
23#if defined(CONFIG_TARTGET_UCP1020T1)
24
25#define CONFIG_UCP1020_REV_1_3
26
27#define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -040028
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -040029#define CONFIG_TSEC1
30#define CONFIG_TSEC3
31#define CONFIG_HAS_ETH0
32#define CONFIG_HAS_ETH1
33#define CONFIG_ETHADDR 00:19:D3:FF:FF:FF
34#define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE
35#define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD
36#define CONFIG_IPADDR 10.80.41.229
37#define CONFIG_SERVERIP 10.80.41.227
38#define CONFIG_NETMASK 255.255.252.0
39#define CONFIG_ETHPRIME "eTSEC3"
40
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -040041#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
42
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -040043#define CONFIG_SYS_L2_SIZE (256 << 10)
44
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -040045#endif
46
47#if defined(CONFIG_TARGET_UCP1020)
48
49#define CONFIG_UCP1020
50#define CONFIG_UCP1020_REV_1_3
51
52#define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR"
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -040053
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -040054#define CONFIG_TSEC1
55#define CONFIG_TSEC2
56#define CONFIG_TSEC3
57#define CONFIG_HAS_ETH0
58#define CONFIG_HAS_ETH1
59#define CONFIG_HAS_ETH2
60#define CONFIG_ETHADDR 00:06:3B:FF:FF:FF
61#define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE
62#define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD
63#define CONFIG_IPADDR 192.168.1.81
64#define CONFIG_IPADDR1 192.168.1.82
65#define CONFIG_IPADDR2 192.168.1.83
66#define CONFIG_SERVERIP 192.168.1.80
67#define CONFIG_GATEWAYIP 102.168.1.1
68#define CONFIG_NETMASK 255.255.255.0
69#define CONFIG_ETHPRIME "eTSEC1"
70
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -040071#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
72
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -040073#define CONFIG_SYS_L2_SIZE (256 << 10)
74
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -040075#endif
76
77#ifdef CONFIG_SDCARD
78#define CONFIG_RAMBOOT_SDCARD
79#define CONFIG_SYS_RAMBOOT
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -040080#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
81#endif
82
83#ifdef CONFIG_SPIFLASH
84#define CONFIG_RAMBOOT_SPIFLASH
85#define CONFIG_SYS_RAMBOOT
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -040086#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
87#endif
88
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -040089#define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000
90
91#ifndef CONFIG_RESET_VECTOR_ADDRESS
92#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
93#endif
94
95#ifndef CONFIG_SYS_MONITOR_BASE
96#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
97#endif
98
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -040099#define CONFIG_ENV_OVERWRITE
100
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400101#define CONFIG_SYS_SATA_MAX_DEVICE 2
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400102#define CONFIG_LBA48
103
104#define CONFIG_SYS_CLK_FREQ 66666666
105#define CONFIG_DDR_CLK_FREQ 66666666
106
107#define CONFIG_HWCONFIG
108
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400109/*
110 * These can be toggled for performance analysis, otherwise use default.
111 */
112#define CONFIG_L2_CACHE
113#define CONFIG_BTB
114
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400115#define CONFIG_ENABLE_36BIT_PHYS
116
117#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
118#define CONFIG_SYS_MEMTEST_END 0x1fffffff
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400119
120#define CONFIG_SYS_CCSRBAR 0xffe00000
121#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
122
123/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
124 SPL code*/
125#ifdef CONFIG_SPL_BUILD
126#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
127#endif
128
129/* DDR Setup */
130#define CONFIG_DDR_ECC_ENABLE
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400131#ifndef CONFIG_DDR_ECC_ENABLE
132#define CONFIG_SYS_DDR_RAW_TIMING
133#define CONFIG_DDR_SPD
134#endif
135#define CONFIG_SYS_SPD_BUS_NUM 1
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400136
137#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
138#define CONFIG_CHIP_SELECTS_PER_CTRL 1
139#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
140#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
141#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
142
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400143#define CONFIG_DIMM_SLOTS_PER_CTLR 1
144
145/* Default settings for DDR3 */
146#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
147#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
148#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
149#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
150#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
151#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
152
153#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
154#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
155#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
156#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
157
158#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
159#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
160#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
161#define CONFIG_SYS_DDR_RCW_1 0x00000000
162#define CONFIG_SYS_DDR_RCW_2 0x00000000
163#ifdef CONFIG_DDR_ECC_ENABLE
164#define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */
165#else
166#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
167#endif
168#define CONFIG_SYS_DDR_CONTROL_2 0x04401050
169#define CONFIG_SYS_DDR_TIMING_4 0x00220001
170#define CONFIG_SYS_DDR_TIMING_5 0x03402400
171
172#define CONFIG_SYS_DDR_TIMING_3 0x00020000
173#define CONFIG_SYS_DDR_TIMING_0 0x00330004
174#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
175#define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
176#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
177#define CONFIG_SYS_DDR_MODE_1 0x40461520
178#define CONFIG_SYS_DDR_MODE_2 0x8000c000
179#define CONFIG_SYS_DDR_INTERVAL 0x0C300000
180
181#undef CONFIG_CLOCKS_IN_MHZ
182
183/*
184 * Memory map
185 *
186 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
187 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2)
188 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
189 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable
190 * (early boot only)
191 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
192 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
193 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
194 */
195
196/*
197 * Local Bus Definitions
198 */
199#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
200#define CONFIG_SYS_FLASH_BASE 0xec000000
201
202#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
203
204#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
205 | BR_PS_16 | BR_V)
206
207#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
208
209#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
210#define CONFIG_SYS_FLASH_QUIET_TEST
211#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
212
213#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
214
215#undef CONFIG_SYS_FLASH_CHECKSUM
216#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
217#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
218
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400219#define CONFIG_SYS_FLASH_EMPTY_INFO
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400220
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400221#define CONFIG_SYS_INIT_RAM_LOCK
222#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
223/* Initial L1 address */
224#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
225#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
226#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
227/* Size of used area in RAM */
228#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
229
230#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
231 GENERATED_GBL_DATA_SIZE)
232#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
233
234#define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */
235#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
236
237#define CONFIG_SYS_PMC_BASE 0xff980000
238#define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
239#define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
240 BR_PS_8 | BR_V)
241#define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
242 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
243 OR_GPCM_EAD)
244
245#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
246#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
247#ifdef CONFIG_NAND_FSL_ELBC
248#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
249#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
250#endif
251
252/* Serial Port - controlled on board with jumper J8
253 * open - index 2
254 * shorted - index 1
255 */
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400256#undef CONFIG_SERIAL_SOFTWARE_FIFO
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400257#define CONFIG_SYS_NS16550_SERIAL
258#define CONFIG_SYS_NS16550_REG_SIZE 1
259#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
260#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
261#define CONFIG_NS16550_MIN_FUNCTIONS
262#endif
263
264#define CONFIG_SYS_BAUDRATE_TABLE \
265 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
266
267#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
268#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
269
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400270/* I2C */
271#define CONFIG_SYS_I2C
272#define CONFIG_SYS_I2C_FSL
273#define CONFIG_SYS_FSL_I2C_SPEED 400000
274#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
275#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
276#define CONFIG_SYS_FSL_I2C2_SPEED 400000
277#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
278#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
279#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
280#define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
281
282#define CONFIG_RTC_DS1337
Chris Packham2bd3cab2017-05-30 12:03:33 +1200283#define CONFIG_RTC_DS1337_NOOSC
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400284#define CONFIG_SYS_I2C_RTC_ADDR 0x68
285#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
286#define CONFIG_SYS_I2C_NCT72_ADDR 0x4C
287#define CONFIG_SYS_I2C_IDT6V49205B 0x69
288
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400289#if defined(CONFIG_PCI)
290/*
291 * General PCI
292 * Memory space is mapped 1-1, but I/O space must start from 0.
293 */
294
295/* controller 2, direct to uli, tgtid 2, Base address 9000 */
296#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9"
297#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
298#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
299#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
300#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
301#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
302#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
303#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
304#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
305
306/* controller 1, Slot 2, tgtid 1, Base address a000 */
307#define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10"
308#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
309#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
310#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
311#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
312#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
313#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
314#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
315#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
316
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400317#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400318#endif /* CONFIG_PCI */
319
320/*
321 * Environment
322 */
323#ifdef CONFIG_ENV_FIT_UCBOOT
324
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400325#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000)
326#define CONFIG_ENV_SIZE 0x20000
327#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
328
329#else
330
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400331
332#ifdef CONFIG_RAMBOOT_SPIFLASH
333
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400334#define CONFIG_ENV_SIZE 0x3000 /* 12KB */
335#define CONFIG_ENV_OFFSET 0x2000 /* 8KB */
336#define CONFIG_ENV_SECT_SIZE 0x1000
337
338#if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
339/* Address and size of Redundant Environment Sector */
340#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
341#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
342#endif
343
344#elif defined(CONFIG_RAMBOOT_SDCARD)
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400345#define CONFIG_FSL_FIXED_MMC_LOCATION
346#define CONFIG_ENV_SIZE 0x2000
347#define CONFIG_SYS_MMC_ENV_DEV 0
348
349#elif defined(CONFIG_SYS_RAMBOOT)
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400350#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
351#define CONFIG_ENV_SIZE 0x2000
352
353#else
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400354#define CONFIG_ENV_BASE (CONFIG_SYS_FLASH_BASE)
355#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
356#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
357#define CONFIG_ENV_ADDR (CONFIG_ENV_BASE + 0xC0000)
358#if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
359/* Address and size of Redundant Environment Sector */
360#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
361#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
362#endif
363
364#endif
365
366#endif /* CONFIG_ENV_FIT_UCBOOT */
367
368#define CONFIG_LOADS_ECHO /* echo on for serial download */
369#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
370
371/*
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400372 * USB
373 */
374#define CONFIG_HAS_FSL_DR_USB
375
376#if defined(CONFIG_HAS_FSL_DR_USB)
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400377#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
378
Tom Rini8850c5d2017-05-12 22:33:27 -0400379#ifdef CONFIG_USB_EHCI_HCD
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400380#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
381#define CONFIG_USB_EHCI_FSL
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400382#endif
383#endif
384
385#undef CONFIG_WATCHDOG /* watchdog disabled */
386
387#ifdef CONFIG_MMC
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400388#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400389#define CONFIG_MMC_SPI
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400390#endif
391
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400392/* Misc Extra Settings */
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400393#undef CONFIG_WATCHDOG /* watchdog disabled */
394
395/*
396 * Miscellaneous configurable options
397 */
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400398#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400399#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
400
401/*
402 * For booting Linux, the board info and command line data
403 * have to be in the first 64 MB of memory, since this is
404 * the maximum mapped by the Linux kernel during initialization.
405 */
406#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
407#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
408
409#if defined(CONFIG_CMD_KGDB)
410#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
411#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
412#endif
413
414/*
415 * Environment Configuration
416 */
417
418#if defined(CONFIG_TSEC_ENET)
419
Alexandru Gagniucfb92bc82017-07-07 11:36:58 -0700420#if defined(CONFIG_UCP1020_REV_1_2) || defined(CONFIG_UCP1020_REV_1_3)
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400421#else
422#error "UCP1020 module revision is not defined !!!"
423#endif
424
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400425#define CONFIG_BOOTP_SERVERIP
426
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400427#define CONFIG_TSEC1_NAME "eTSEC1"
428#define CONFIG_TSEC2_NAME "eTSEC2"
429#define CONFIG_TSEC3_NAME "eTSEC3"
430
431#define TSEC1_PHY_ADDR 4
432#define TSEC2_PHY_ADDR 0
433#define TSEC2_PHY_ADDR_SGMII 0x00
434#define TSEC3_PHY_ADDR 6
435
436#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
437#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
438#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
439
440#define TSEC1_PHYIDX 0
441#define TSEC2_PHYIDX 0
442#define TSEC3_PHYIDX 0
443
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400444#endif
445
Mario Six5bc05432018-03-28 14:38:20 +0200446#define CONFIG_HOSTNAME "UCP1020"
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400447#define CONFIG_ROOTPATH "/opt/nfsroot"
448#define CONFIG_BOOTFILE "uImage"
449#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
450
451/* default location for tftp and bootm */
452#define CONFIG_LOADADDR 1000000
453
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400454#if defined(CONFIG_DONGLE)
455
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400456#define CONFIG_EXTRA_ENV_SETTINGS \
457"bootcmd=run prog_spi_mbrbootcramfs\0" \
458"bootfile=uImage\0" \
459"consoledev=ttyS0\0" \
460"cramfsfile=image.cramfs\0" \
461"dtbaddr=0x00c00000\0" \
462"dtbfile=image.dtb\0" \
463"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
464"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
465"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
466"fileaddr=0x01000000\0" \
467"filesize=0x00080000\0" \
468"flashmbr=sf probe 0; " \
469 "tftp $loadaddr $mbr; " \
470 "sf erase $mbr_offset +$filesize; " \
471 "sf write $loadaddr $mbr_offset $filesize\0" \
472"flashrecovery=tftp $recoveryaddr $cramfsfile; " \
473 "protect off $nor_recoveryaddr +$filesize; " \
474 "erase $nor_recoveryaddr +$filesize; " \
475 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
476 "protect on $nor_recoveryaddr +$filesize\0 " \
477"flashuboot=tftp $ubootaddr $ubootfile; " \
478 "protect off $nor_ubootaddr +$filesize; " \
479 "erase $nor_ubootaddr +$filesize; " \
480 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
481 "protect on $nor_ubootaddr +$filesize\0 " \
482"flashworking=tftp $workingaddr $cramfsfile; " \
483 "protect off $nor_workingaddr +$filesize; " \
484 "erase $nor_workingaddr +$filesize; " \
485 "cp.b $workingaddr $nor_workingaddr $filesize; " \
486 "protect on $nor_workingaddr +$filesize\0 " \
487"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
488"kerneladdr=0x01100000\0" \
489"kernelfile=uImage\0" \
490"loadaddr=0x01000000\0" \
491"mbr=uCP1020d.mbr\0" \
492"mbr_offset=0x00000000\0" \
493"mmbr=uCP1020Quiet.mbr\0" \
494"mmcpart=0:2\0" \
495"mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
496 "mmc erase 1 1; " \
497 "mmc write $loadaddr 1 1\0" \
498"mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \
499 "mmc erase 0x40 0x400; " \
500 "mmc write $loadaddr 0x40 0x400\0" \
501"netdev=eth0\0" \
502"nor_recoveryaddr=0xEC0A0000\0" \
503"nor_ubootaddr=0xEFF80000\0" \
504"nor_workingaddr=0xECFA0000\0" \
505"norbootrecovery=setenv bootargs $recoverybootargs" \
506 " console=$consoledev,$baudrate $othbootargs; " \
507 "run norloadrecovery; " \
508 "bootm $kerneladdr - $dtbaddr\0" \
509"norbootworking=setenv bootargs $workingbootargs" \
510 " console=$consoledev,$baudrate $othbootargs; " \
511 "run norloadworking; " \
512 "bootm $kerneladdr - $dtbaddr\0" \
513"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
514 "setenv cramfsaddr $nor_recoveryaddr; " \
515 "cramfsload $dtbaddr $dtbfile; " \
516 "cramfsload $kerneladdr $kernelfile\0" \
517"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
518 "setenv cramfsaddr $nor_workingaddr; " \
519 "cramfsload $dtbaddr $dtbfile; " \
520 "cramfsload $kerneladdr $kernelfile\0" \
521"prog_spi_mbr=run spi__mbr\0" \
522"prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \
523"prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \
524 "run spi__cramfs\0" \
525"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
526 " console=$consoledev,$baudrate $othbootargs; " \
527 "tftp $rootfsaddr $rootfsfile; " \
528 "tftp $loadaddr $kernelfile; " \
529 "tftp $dtbaddr $dtbfile; " \
530 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
531"ramdisk_size=120000\0" \
532"ramdiskfile=rootfs.ext2.gz.uboot\0" \
533"recoveryaddr=0x02F00000\0" \
534"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
535"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
536 "mw.l 0xffe0f008 0x00400000\0" \
537"rootfsaddr=0x02F00000\0" \
538"rootfsfile=rootfs.ext2.gz.uboot\0" \
539"rootpath=/opt/nfsroot\0" \
540"spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
541 "protect off 0xeC000000 +$filesize; " \
542 "erase 0xEC000000 +$filesize; " \
543 "cp.b $loadaddr 0xEC000000 $filesize; " \
544 "cmp.b $loadaddr 0xEC000000 $filesize; " \
545 "protect on 0xeC000000 +$filesize\0" \
546"spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
547 "protect off 0xeFF80000 +$filesize; " \
548 "erase 0xEFF80000 +$filesize; " \
549 "cp.b $loadaddr 0xEFF80000 $filesize; " \
550 "cmp.b $loadaddr 0xEFF80000 $filesize; " \
551 "protect on 0xeFF80000 +$filesize\0" \
552"spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \
553 "sf probe 0; sf erase 0x8000 +$filesize; " \
554 "sf write $loadaddr 0x8000 $filesize\0" \
555"spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \
556 "protect off 0xec0a0000 +$filesize; " \
557 "erase 0xeC0A0000 +$filesize; " \
558 "cp.b $loadaddr 0xeC0A0000 $filesize; " \
559 "protect on 0xec0a0000 +$filesize\0" \
560"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
561 "sf probe 1; sf erase 0 +$filesize; " \
562 "sf write $loadaddr 0 $filesize\0" \
563"spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
564 "sf probe 0; sf erase 0 +$filesize; " \
565 "sf write $loadaddr 0 $filesize\0" \
566"tftpflash=tftpboot $loadaddr $uboot; " \
567 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
568 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
569 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
570 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
571 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
572"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
573"ubootaddr=0x01000000\0" \
574"ubootfile=u-boot.bin\0" \
575"ubootd=u-boot4dongle.bin\0" \
576"upgrade=run flashworking\0" \
577"usb_phy_type=ulpi\0 " \
578"workingaddr=0x02F00000\0" \
579"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
580
581#else
582
583#if defined(CONFIG_UCP1020T1)
584
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400585#define CONFIG_EXTRA_ENV_SETTINGS \
586"bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \
587"bootfile=uImage\0" \
588"consoledev=ttyS0\0" \
589"cramfsfile=image.cramfs\0" \
590"dtbaddr=0x00c00000\0" \
591"dtbfile=image.dtb\0" \
592"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
593"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
594"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
595"fileaddr=0x01000000\0" \
596"filesize=0x00080000\0" \
597"flashmbr=sf probe 0; " \
598 "tftp $loadaddr $mbr; " \
599 "sf erase $mbr_offset +$filesize; " \
600 "sf write $loadaddr $mbr_offset $filesize\0" \
601"flashrecovery=tftp $recoveryaddr $cramfsfile; " \
602 "protect off $nor_recoveryaddr +$filesize; " \
603 "erase $nor_recoveryaddr +$filesize; " \
604 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
605 "protect on $nor_recoveryaddr +$filesize\0 " \
606"flashuboot=tftp $ubootaddr $ubootfile; " \
607 "protect off $nor_ubootaddr +$filesize; " \
608 "erase $nor_ubootaddr +$filesize; " \
609 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
610 "protect on $nor_ubootaddr +$filesize\0 " \
611"flashworking=tftp $workingaddr $cramfsfile; " \
612 "protect off $nor_workingaddr +$filesize; " \
613 "erase $nor_workingaddr +$filesize; " \
614 "cp.b $workingaddr $nor_workingaddr $filesize; " \
615 "protect on $nor_workingaddr +$filesize\0 " \
616"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
617"kerneladdr=0x01100000\0" \
618"kernelfile=uImage\0" \
619"loadaddr=0x01000000\0" \
620"mbr=uCP1020.mbr\0" \
621"mbr_offset=0x00000000\0" \
622"netdev=eth0\0" \
623"nor_recoveryaddr=0xEC0A0000\0" \
624"nor_ubootaddr=0xEFF80000\0" \
625"nor_workingaddr=0xECFA0000\0" \
626"norbootrecovery=setenv bootargs $recoverybootargs" \
627 " console=$consoledev,$baudrate $othbootargs; " \
628 "run norloadrecovery; " \
629 "bootm $kerneladdr - $dtbaddr\0" \
630"norbootworking=setenv bootargs $workingbootargs" \
631 " console=$consoledev,$baudrate $othbootargs; " \
632 "run norloadworking; " \
633 "bootm $kerneladdr - $dtbaddr\0" \
634"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
635 "setenv cramfsaddr $nor_recoveryaddr; " \
636 "cramfsload $dtbaddr $dtbfile; " \
637 "cramfsload $kerneladdr $kernelfile\0" \
638"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
639 "setenv cramfsaddr $nor_workingaddr; " \
640 "cramfsload $dtbaddr $dtbfile; " \
641 "cramfsload $kerneladdr $kernelfile\0" \
642"othbootargs=quiet\0" \
643"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
644 " console=$consoledev,$baudrate $othbootargs; " \
645 "tftp $rootfsaddr $rootfsfile; " \
646 "tftp $loadaddr $kernelfile; " \
647 "tftp $dtbaddr $dtbfile; " \
648 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
649"ramdisk_size=120000\0" \
650"ramdiskfile=rootfs.ext2.gz.uboot\0" \
651"recoveryaddr=0x02F00000\0" \
652"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
653"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
654 "mw.l 0xffe0f008 0x00400000\0" \
655"rootfsaddr=0x02F00000\0" \
656"rootfsfile=rootfs.ext2.gz.uboot\0" \
657"rootpath=/opt/nfsroot\0" \
658"silent=1\0" \
659"tftpflash=tftpboot $loadaddr $uboot; " \
660 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
661 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
662 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
663 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
664 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
665"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
666"ubootaddr=0x01000000\0" \
667"ubootfile=u-boot.bin\0" \
668"upgrade=run flashworking\0" \
669"workingaddr=0x02F00000\0" \
670"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
671
672#else /* For Arcturus Modules */
673
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400674#define CONFIG_EXTRA_ENV_SETTINGS \
675"bootcmd=run norkernel\0" \
676"bootfile=uImage\0" \
677"consoledev=ttyS0\0" \
678"dtbaddr=0x00c00000\0" \
679"dtbfile=image.dtb\0" \
680"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
681"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
682"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
683"fileaddr=0x01000000\0" \
684"filesize=0x00080000\0" \
685"flashmbr=sf probe 0; " \
686 "tftp $loadaddr $mbr; " \
687 "sf erase $mbr_offset +$filesize; " \
688 "sf write $loadaddr $mbr_offset $filesize\0" \
689"flashuboot=tftp $loadaddr $ubootfile; " \
690 "protect off $nor_ubootaddr0 +$filesize; " \
691 "erase $nor_ubootaddr0 +$filesize; " \
692 "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \
693 "protect on $nor_ubootaddr0 +$filesize; " \
694 "protect off $nor_ubootaddr1 +$filesize; " \
695 "erase $nor_ubootaddr1 +$filesize; " \
696 "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \
697 "protect on $nor_ubootaddr1 +$filesize\0 " \
698"format0=protect off $part0base +$part0size; " \
699 "erase $part0base +$part0size\0" \
700"format1=protect off $part1base +$part1size; " \
701 "erase $part1base +$part1size\0" \
702"format2=protect off $part2base +$part2size; " \
703 "erase $part2base +$part2size\0" \
704"format3=protect off $part3base +$part3size; " \
705 "erase $part3base +$part3size\0" \
706"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
707"kerneladdr=0x01100000\0" \
708"kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \
709"kernelfile=uImage\0" \
710"loadaddr=0x01000000\0" \
711"mbr=uCP1020.mbr\0" \
712"mbr_offset=0x00000000\0" \
713"netdev=eth0\0" \
714"nor_ubootaddr0=0xEC000000\0" \
715"nor_ubootaddr1=0xEFF80000\0" \
716"norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \
717 "run norkernelload; " \
718 "bootm $kerneladdr - $dtbaddr\0" \
719"norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \
720 "setenv cramfsaddr $part0base; " \
721 "cramfsload $dtbaddr $dtbfile; " \
722 "cramfsload $kerneladdr $kernelfile\0" \
723"part0base=0xEC100000\0" \
724"part0size=0x00700000\0" \
725"part1base=0xEC800000\0" \
726"part1size=0x02000000\0" \
727"part2base=0xEE800000\0" \
728"part2size=0x00800000\0" \
729"part3base=0xEF000000\0" \
730"part3size=0x00F80000\0" \
731"partENVbase=0xEC080000\0" \
732"partENVsize=0x00080000\0" \
733"program0=tftp part0-000000.bin; " \
734 "protect off $part0base +$filesize; " \
735 "erase $part0base +$filesize; " \
736 "cp.b $loadaddr $part0base $filesize; " \
737 "echo Verifying...; " \
738 "cmp.b $loadaddr $part0base $filesize\0" \
739"program1=tftp part1-000000.bin; " \
740 "protect off $part1base +$filesize; " \
741 "erase $part1base +$filesize; " \
742 "cp.b $loadaddr $part1base $filesize; " \
743 "echo Verifying...; " \
744 "cmp.b $loadaddr $part1base $filesize\0" \
745"program2=tftp part2-000000.bin; " \
746 "protect off $part2base +$filesize; " \
747 "erase $part2base +$filesize; " \
748 "cp.b $loadaddr $part2base $filesize; " \
749 "echo Verifying...; " \
750 "cmp.b $loadaddr $part2base $filesize\0" \
751"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
752 " console=$consoledev,$baudrate $othbootargs; " \
753 "tftp $rootfsaddr $rootfsfile; " \
754 "tftp $loadaddr $kernelfile; " \
755 "tftp $dtbaddr $dtbfile; " \
756 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
757"ramdisk_size=120000\0" \
758"ramdiskfile=rootfs.ext2.gz.uboot\0" \
759"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
760 "mw.l 0xffe0f008 0x00400000\0" \
761"rootfsaddr=0x02F00000\0" \
762"rootfsfile=rootfs.ext2.gz.uboot\0" \
763"rootpath=/opt/nfsroot\0" \
764"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
765 "sf probe 0; sf erase 0 +$filesize; " \
766 "sf write $loadaddr 0 $filesize\0" \
767"spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
768 "protect off 0xeC000000 +$filesize; " \
769 "erase 0xEC000000 +$filesize; " \
770 "cp.b $loadaddr 0xEC000000 $filesize; " \
771 "cmp.b $loadaddr 0xEC000000 $filesize; " \
772 "protect on 0xeC000000 +$filesize\0" \
773"tftpflash=tftpboot $loadaddr $uboot; " \
774 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
775 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
776 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
777 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
778 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
779"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
780"ubootfile=u-boot.bin\0" \
781"upgrade=run flashuboot\0" \
782"usb_phy_type=ulpi\0 " \
783"boot_nfs= " \
784 "setenv bootargs root=/dev/nfs rw " \
785 "nfsroot=$serverip:$rootpath " \
786 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
787 "console=$consoledev,$baudrate $othbootargs;" \
788 "tftp $loadaddr $bootfile;" \
789 "tftp $fdtaddr $fdtfile;" \
790 "bootm $loadaddr - $fdtaddr\0" \
791"boot_hd = " \
792 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
793 "console=$consoledev,$baudrate $othbootargs;" \
794 "usb start;" \
795 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
796 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
797 "bootm $loadaddr - $fdtaddr\0" \
798"boot_usb_fat = " \
799 "setenv bootargs root=/dev/ram rw " \
800 "console=$consoledev,$baudrate $othbootargs " \
801 "ramdisk_size=$ramdisk_size;" \
802 "usb start;" \
803 "fatload usb 0:2 $loadaddr $bootfile;" \
804 "fatload usb 0:2 $fdtaddr $fdtfile;" \
805 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
806 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
807"boot_usb_ext2 = " \
808 "setenv bootargs root=/dev/ram rw " \
809 "console=$consoledev,$baudrate $othbootargs " \
810 "ramdisk_size=$ramdisk_size;" \
811 "usb start;" \
812 "ext2load usb 0:4 $loadaddr $bootfile;" \
813 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
814 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
815 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
816"boot_nor = " \
817 "setenv bootargs root=/dev/$jffs2nor rw " \
818 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
819 "bootm $norbootaddr - $norfdtaddr\0 " \
820"boot_ram = " \
821 "setenv bootargs root=/dev/ram rw " \
822 "console=$consoledev,$baudrate $othbootargs " \
823 "ramdisk_size=$ramdisk_size;" \
824 "tftp $ramdiskaddr $ramdiskfile;" \
825 "tftp $loadaddr $bootfile;" \
826 "tftp $fdtaddr $fdtfile;" \
827 "bootm $loadaddr $ramdiskaddr $fdtaddr\0"
828
829#endif
830#endif
831
832#endif /* __CONFIG_H */