blob: d5cb3e4df97293ce897ba33c55cf46eddae913aa [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
York Sunf749db32014-06-23 15:15:56 -07002/*
3 * Copyright 2014 Freescale Semiconductor
York Sunf749db32014-06-23 15:15:56 -07004 */
5
6#ifndef __LS2_EMU_H
7#define __LS2_EMU_H
8
Prabhakar Kushwaha44937212015-11-09 16:42:07 +05309#include "ls2080a_common.h"
York Sunf749db32014-06-23 15:15:56 -070010
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -070011#define CONFIG_SYS_CLK_FREQ 100000000
12#define CONFIG_DDR_CLK_FREQ 133333333
13
York Sunf749db32014-06-23 15:15:56 -070014#define CONFIG_DDR_SPD
15#define CONFIG_SYS_FSL_DDR_EMU /* Support emulator */
16#define SPD_EEPROM_ADDRESS1 0x51
17#define SPD_EEPROM_ADDRESS2 0x52
York Sund9c68b12014-08-13 10:21:05 -070018#define SPD_EEPROM_ADDRESS3 0x53
York Sunf749db32014-06-23 15:15:56 -070019#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
20#define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD on I2C bus 1 */
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -070021#define CONFIG_DIMM_SLOTS_PER_CTLR 1
22#define CONFIG_CHIP_SELECTS_PER_CTRL 4
Prabhakar Kushwaha44937212015-11-09 16:42:07 +053023#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -070024#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
Prabhakar Kushwaha44937212015-11-09 16:42:07 +053025#endif
York Sunf749db32014-06-23 15:15:56 -070026
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -070027#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
28#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
29/*
30 * NOR Flash Timing Params
31 */
32#define CONFIG_SYS_NOR0_CSPR \
33 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
34 CSPR_PORT_SIZE_16 | \
35 CSPR_MSEL_NOR | \
36 CSPR_V)
37#define CONFIG_SYS_NOR0_CSPR_EARLY \
38 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
39 CSPR_PORT_SIZE_16 | \
40 CSPR_MSEL_NOR | \
41 CSPR_V)
42#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
43#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
44 FTIM0_NOR_TEADC(0x1) | \
45 FTIM0_NOR_TEAHC(0x1))
46#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
47 FTIM1_NOR_TRAD_NOR(0x1))
48#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
49 FTIM2_NOR_TCH(0x0) | \
50 FTIM2_NOR_TWP(0x1))
51#define CONFIG_SYS_NOR_FTIM3 0x04000000
52#define CONFIG_SYS_IFC_CCR 0x01000000
53
54#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
55#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
56#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
57#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
58#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
59#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
60#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
61#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
62#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
63
64/* Debug Server firmware */
65#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
66#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL
67
J. German Rivera125e2bc2015-03-20 19:28:18 -070068/*
69 * This trick allows users to load MC images into DDR directly without
70 * copying from NOR flash. It dramatically improves speed.
71 */
72#define CONFIG_SYS_LS_MC_FW_IN_DDR
73#define CONFIG_SYS_LS_MC_DPL_IN_DDR
74#define CONFIG_SYS_LS_MC_DPC_IN_DDR
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -070075
J. German Rivera125e2bc2015-03-20 19:28:18 -070076#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -070077
78/* Store environment at top of flash */
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -070079#define CONFIG_ENV_SIZE 0x1000
80
York Sunf749db32014-06-23 15:15:56 -070081#endif /* __LS2_EMU_H */