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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +05302/*
3 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 * Based on davinci_dvevm.h. Original Copyrights follow:
6 *
7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +05308 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13/*
14 * Board
15 */
16
17/*
18 * SoC Configuration
19 */
Tom Rini65cc0e22022-11-16 13:10:41 -050020#define CFG_SYS_EXCEPTION_VECTORS_HIGH
21#define CFG_SYS_OSCIN_FREQ 24000000
22#define CFG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
23#define CFG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053024
Adam Ford7bb33e42020-06-29 18:49:41 -050025#ifdef CONFIG_MTD_NOR_FLASH
Tom Rini65cc0e22022-11-16 13:10:41 -050026#define CFG_SYS_DV_NOR_BOOT_CFG (0x11)
Lad, Prabhakar63777662012-06-24 21:35:23 +000027#endif
28
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053029/*
30 * Memory Info
31 */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053032#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
33#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
Tom Rini8a897c42022-12-04 10:04:51 -050034#define CFG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053035/* memtest start addr */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053036
37/* memtest will be run on 16MB */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053038
Tom Rini65cc0e22022-11-16 13:10:41 -050039#define CFG_SYS_DA850_SYSCFG_SUSPSRC ( \
Christian Riesch3d2c8e62011-12-09 09:47:37 +000040 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
41 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
42 DAVINCI_SYSCFG_SUSPSRC_UART2 | \
43 DAVINCI_SYSCFG_SUSPSRC_EMAC | \
44 DAVINCI_SYSCFG_SUSPSRC_I2C)
45
46/*
47 * PLL configuration
48 */
Christian Riesch3d2c8e62011-12-09 09:47:37 +000049
Tom Rini65cc0e22022-11-16 13:10:41 -050050#define CFG_SYS_DA850_PLL0_PLLM 24
51#define CFG_SYS_DA850_PLL1_PLLM 21
Christian Riesch3d2c8e62011-12-09 09:47:37 +000052
53/*
54 * DDR2 memory configuration
55 */
Tom Rini65cc0e22022-11-16 13:10:41 -050056#define CFG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
Christian Riesch3d2c8e62011-12-09 09:47:37 +000057 DV_DDR_PHY_EXT_STRBEN | \
58 (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
59
Tom Rini65cc0e22022-11-16 13:10:41 -050060#define CFG_SYS_DA850_DDR2_SDBCR ( \
Christian Riesch3d2c8e62011-12-09 09:47:37 +000061 (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
62 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
63 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
64 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
65 (0x3 << DV_DDR_SDCR_CL_SHIFT) | \
66 (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \
67 (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
68
69/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
Tom Rini65cc0e22022-11-16 13:10:41 -050070#define CFG_SYS_DA850_DDR2_SDBCR2 0
Christian Riesch3d2c8e62011-12-09 09:47:37 +000071
Tom Rini65cc0e22022-11-16 13:10:41 -050072#define CFG_SYS_DA850_DDR2_SDTIMR ( \
Christian Riesch3d2c8e62011-12-09 09:47:37 +000073 (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \
74 (2 << DV_DDR_SDTMR1_RP_SHIFT) | \
75 (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \
76 (1 << DV_DDR_SDTMR1_WR_SHIFT) | \
77 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
78 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
79 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
80 (0 << DV_DDR_SDTMR1_WTR_SHIFT))
81
Tom Rini65cc0e22022-11-16 13:10:41 -050082#define CFG_SYS_DA850_DDR2_SDTIMR2 ( \
Christian Riesch3d2c8e62011-12-09 09:47:37 +000083 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
84 (0 << DV_DDR_SDTMR2_XP_SHIFT) | \
85 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
86 (17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
87 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
88 (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
89 (0 << DV_DDR_SDTMR2_CKE_SHIFT))
90
Tom Rini65cc0e22022-11-16 13:10:41 -050091#define CFG_SYS_DA850_DDR2_SDRCR 0x00000494
92#define CFG_SYS_DA850_DDR2_PBBPR 0x30
Christian Riesch3d2c8e62011-12-09 09:47:37 +000093
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053094/*
95 * Serial Driver info
96 */
Tom Rini91092132022-11-16 13:10:28 -050097#define CFG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053098
Tom Rini65cc0e22022-11-16 13:10:41 -050099#define CFG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
Stefano Babicd73a8a12010-11-11 15:38:02 +0100100
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530101/*
102 * I2C Configuration
103 */
Tom Rini65cc0e22022-11-16 13:10:41 -0500104#define CFG_SYS_I2C_EXPANDER_ADDR 0x20
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530105
106/*
Ben Gardiner6b2c6462010-10-14 17:26:25 -0400107 * Flash & Environment
108 */
Miquel Raynal88718be2019-10-03 19:50:03 +0200109#ifdef CONFIG_MTD_RAW_NAND
Tom Rini4e590942022-11-12 17:36:51 -0500110#define CFG_SYS_NAND_CS 3
111#define CFG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
112#define CFG_SYS_NAND_MASK_CLE 0x10
113#define CFG_SYS_NAND_MASK_ALE 0x8
114#define CFG_SYS_NAND_U_BOOT_SIZE 0x40000
115#define CFG_SYS_NAND_U_BOOT_DST 0xc1080000
116#define CFG_SYS_NAND_U_BOOT_START CFG_SYS_NAND_U_BOOT_DST
117#define CFG_SYS_NAND_ECCPOS { \
Lad, Prabhakar122f9c92012-06-24 21:35:22 +0000118 24, 25, 26, 27, 28, \
119 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
120 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
121 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
122 59, 60, 61, 62, 63 }
Tom Rini4e590942022-11-12 17:36:51 -0500123#define CFG_SYS_NAND_ECCSIZE 512
124#define CFG_SYS_NAND_ECCBYTES 10
Ben Gardiner6b2c6462010-10-14 17:26:25 -0400125#endif
126
Adam Ford7bb33e42020-06-29 18:49:41 -0500127#ifdef CONFIG_MTD_NOR_FLASH
Tom Rini65cc0e22022-11-16 13:10:41 -0500128#define CFG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
Nagabhushana Netagunte1506b0a2011-09-03 22:18:32 -0400129#define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */
Adam Ford93f33622018-08-15 13:22:03 -0500130#endif
Stefano Babicd73a8a12010-11-11 15:38:02 +0100131
Ben Gardiner3d248d32010-10-14 17:26:29 -0400132/*
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530133 * U-Boot general configuration
134 */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530135
136/*
137 * Linux Information
138 */
Ben Gardiner59e0d612010-10-14 17:26:32 -0400139#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
Adam Forda4670f82017-09-17 20:43:46 -0500140
Adam Forda4670f82017-09-17 20:43:46 -0500141#define DEFAULT_LINUX_BOOT_ENV \
142 "loadaddr=0xc0700000\0" \
143 "fdtaddr=0xc0600000\0" \
144 "scriptaddr=0xc0600000\0"
145
146#include <environment/ti/mmc.h>
147
Tom Rini0613c362022-12-04 10:03:50 -0500148#define CFG_EXTRA_ENV_SETTINGS \
Adam Forda4670f82017-09-17 20:43:46 -0500149 DEFAULT_LINUX_BOOT_ENV \
150 DEFAULT_MMC_TI_ARGS \
151 "bootpart=0:2\0" \
152 "bootdir=/boot\0" \
153 "bootfile=zImage\0" \
154 "fdtfile=da850-evm.dtb\0" \
155 "boot_fdt=yes\0" \
156 "boot_fit=0\0" \
157 "console=ttyS2,115200n8\0" \
158 "hwconfig=dsp:wake=yes"
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530159
Adam Ford7bb33e42020-06-29 18:49:41 -0500160#ifdef CONFIG_SPL_BUILD
Christian Riesch3d2c8e62011-12-09 09:47:37 +0000161/* defines for SPL */
Adam Forda69c4892021-03-05 20:48:50 -0600162
Lad, Prabhakar63777662012-06-24 21:35:23 +0000163#endif
Lad, Prabhakar0d986e62012-06-24 21:35:20 +0000164
165/* Load U-Boot Image From MMC */
Lad, Prabhakar0d986e62012-06-24 21:35:20 +0000166
Heiko Schocherab86f722010-09-17 13:10:42 +0200167/* additions for new relocation code, must added to all boards */
Tom Riniaa6e94d2022-11-16 13:10:37 -0500168#define CFG_SYS_SDRAM_BASE 0xc0000000
Lad, Prabhakar63777662012-06-24 21:35:23 +0000169
Simon Glass89f5eaa2017-05-17 08:23:09 -0600170#include <asm/arch/hardware.h>
171
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530172#endif /* __CONFIG_H */