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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Vikas Manocha6a12ceb2016-02-11 15:47:19 -08002/*
Patrice Chotard3bc599c2017-10-23 09:53:58 +02003 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
4 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
Vikas Manocha6a12ceb2016-02-11 15:47:19 -08005 */
6
Patrice Chotardae74de02018-01-12 09:23:49 +01007#ifndef _SERIAL_STM32_
8#define _SERIAL_STM32_
Vikas Manocha6a12ceb2016-02-11 15:47:19 -08009
Simon Glasscd93d622020-05-10 11:40:13 -060010#include <linux/bitops.h>
Patrice Chotard60a996b2017-09-27 15:44:50 +020011#define CR1_OFFSET(x) (x ? 0x0c : 0x00)
12#define CR3_OFFSET(x) (x ? 0x14 : 0x08)
13#define BRR_OFFSET(x) (x ? 0x08 : 0x0c)
14#define ISR_OFFSET(x) (x ? 0x00 : 0x1c)
Patrice Chotard7b3b74d2018-04-20 08:59:06 +020015
16#define ICR_OFFSET 0x20
Patrick Delaunaybc709a42018-05-17 14:50:45 +020017
Patrice Chotard60a996b2017-09-27 15:44:50 +020018/*
19 * STM32F4 has one Data Register (DR) for received or transmitted
20 * data, so map Receive Data Register (RDR) and Transmit Data
21 * Register (TDR) at the same offset
22 */
23#define RDR_OFFSET(x) (x ? 0x04 : 0x24)
24#define TDR_OFFSET(x) (x ? 0x04 : 0x28)
25
26struct stm32_uart_info {
27 u8 uart_enable_bit; /* UART_CR1_UE */
28 bool stm32f4; /* true for STM32F4, false otherwise */
Patrice Chotard2a7ecc52017-09-27 15:44:51 +020029 bool has_fifo;
Patrice Chotard60a996b2017-09-27 15:44:50 +020030};
31
Patrice Chotard6c30f152017-09-27 15:44:52 +020032struct stm32_uart_info stm32f4_info = {
33 .stm32f4 = true,
34 .uart_enable_bit = 13,
Patrice Chotard6c30f152017-09-27 15:44:52 +020035 .has_fifo = false,
36};
37
Patrice Chotard2a7ecc52017-09-27 15:44:51 +020038struct stm32_uart_info stm32f7_info = {
Patrice Chotard60a996b2017-09-27 15:44:50 +020039 .uart_enable_bit = 0,
40 .stm32f4 = false,
Patrice Chotard95a07722018-09-20 15:14:15 +020041 .has_fifo = true,
Patrice Chotard2a7ecc52017-09-27 15:44:51 +020042};
43
44struct stm32_uart_info stm32h7_info = {
45 .uart_enable_bit = 0,
46 .stm32f4 = false,
Patrice Chotard2a7ecc52017-09-27 15:44:51 +020047 .has_fifo = true,
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080048};
49
Patrice Chotard122b2d42017-07-18 09:29:07 +020050/* Information about a serial port */
51struct stm32x7_serial_platdata {
Patrice Chotard60a996b2017-09-27 15:44:50 +020052 fdt_addr_t base; /* address of registers in physical memory */
53 struct stm32_uart_info *uart_info;
Patrice Chotard27265ce2017-07-18 09:29:08 +020054 unsigned long int clock_rate;
Patrice Chotard122b2d42017-07-18 09:29:07 +020055};
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080056
Patrice Chotard2a7ecc52017-09-27 15:44:51 +020057#define USART_CR1_FIFOEN BIT(29)
Patrick Delaunaybc709a42018-05-17 14:50:45 +020058#define USART_CR1_M1 BIT(28)
Patrice Chotard2a52a952017-09-27 15:44:48 +020059#define USART_CR1_OVER8 BIT(15)
Patrick Delaunaybc709a42018-05-17 14:50:45 +020060#define USART_CR1_M0 BIT(12)
61#define USART_CR1_PCE BIT(10)
62#define USART_CR1_PS BIT(9)
Patrice Chotard2a52a952017-09-27 15:44:48 +020063#define USART_CR1_TE BIT(3)
64#define USART_CR1_RE BIT(2)
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080065
Patrice Chotard2a52a952017-09-27 15:44:48 +020066#define USART_CR3_OVRDIS BIT(12)
Vikas Manocha6c0c3ce2017-05-28 12:55:12 -070067
Patrice Chotardbe1a6f72018-05-17 14:50:43 +020068#define USART_ISR_TXE BIT(7)
69#define USART_ISR_RXNE BIT(5)
70#define USART_ISR_ORE BIT(3)
Patrick Delaunay132518f2019-07-30 19:16:46 +020071#define USART_ISR_FE BIT(1)
Patrick Delaunaybc709a42018-05-17 14:50:45 +020072#define USART_ISR_PE BIT(0)
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080073
Patrice Chotard2a52a952017-09-27 15:44:48 +020074#define USART_BRR_F_MASK GENMASK(7, 0)
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080075#define USART_BRR_M_SHIFT 4
Patrice Chotard2a52a952017-09-27 15:44:48 +020076#define USART_BRR_M_MASK GENMASK(15, 4)
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080077
Patrice Chotardbe1a6f72018-05-17 14:50:43 +020078#define USART_ICR_ORECF BIT(3)
Patrick Delaunay132518f2019-07-30 19:16:46 +020079#define USART_ICR_FECF BIT(1)
Patrick Delaunaybc709a42018-05-17 14:50:45 +020080#define USART_ICR_PCECF BIT(0)
81
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080082#endif