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Vikas Manocha6a12ceb2016-02-11 15:47:19 -08001/*
Patrice Chotard3bc599c2017-10-23 09:53:58 +02002 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
3 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
Vikas Manocha6a12ceb2016-02-11 15:47:19 -08004 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
Patrice Chotardae74de02018-01-12 09:23:49 +01008#ifndef _SERIAL_STM32_
9#define _SERIAL_STM32_
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080010
Patrice Chotard60a996b2017-09-27 15:44:50 +020011#define CR1_OFFSET(x) (x ? 0x0c : 0x00)
12#define CR3_OFFSET(x) (x ? 0x14 : 0x08)
13#define BRR_OFFSET(x) (x ? 0x08 : 0x0c)
14#define ISR_OFFSET(x) (x ? 0x00 : 0x1c)
15/*
16 * STM32F4 has one Data Register (DR) for received or transmitted
17 * data, so map Receive Data Register (RDR) and Transmit Data
18 * Register (TDR) at the same offset
19 */
20#define RDR_OFFSET(x) (x ? 0x04 : 0x24)
21#define TDR_OFFSET(x) (x ? 0x04 : 0x28)
22
23struct stm32_uart_info {
24 u8 uart_enable_bit; /* UART_CR1_UE */
25 bool stm32f4; /* true for STM32F4, false otherwise */
26 bool has_overrun_disable;
Patrice Chotard2a7ecc52017-09-27 15:44:51 +020027 bool has_fifo;
Patrice Chotard60a996b2017-09-27 15:44:50 +020028};
29
Patrice Chotard6c30f152017-09-27 15:44:52 +020030struct stm32_uart_info stm32f4_info = {
31 .stm32f4 = true,
32 .uart_enable_bit = 13,
33 .has_overrun_disable = false,
34 .has_fifo = false,
35};
36
Patrice Chotard2a7ecc52017-09-27 15:44:51 +020037struct stm32_uart_info stm32f7_info = {
Patrice Chotard60a996b2017-09-27 15:44:50 +020038 .uart_enable_bit = 0,
39 .stm32f4 = false,
40 .has_overrun_disable = true,
Patrice Chotard2a7ecc52017-09-27 15:44:51 +020041 .has_fifo = false,
42};
43
44struct stm32_uart_info stm32h7_info = {
45 .uart_enable_bit = 0,
46 .stm32f4 = false,
47 .has_overrun_disable = true,
48 .has_fifo = true,
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080049};
50
Patrice Chotard122b2d42017-07-18 09:29:07 +020051/* Information about a serial port */
52struct stm32x7_serial_platdata {
Patrice Chotard60a996b2017-09-27 15:44:50 +020053 fdt_addr_t base; /* address of registers in physical memory */
54 struct stm32_uart_info *uart_info;
Patrice Chotard27265ce2017-07-18 09:29:08 +020055 unsigned long int clock_rate;
Patrice Chotard122b2d42017-07-18 09:29:07 +020056};
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080057
Patrice Chotard2a7ecc52017-09-27 15:44:51 +020058#define USART_CR1_FIFOEN BIT(29)
Patrice Chotard2a52a952017-09-27 15:44:48 +020059#define USART_CR1_OVER8 BIT(15)
60#define USART_CR1_TE BIT(3)
61#define USART_CR1_RE BIT(2)
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080062
Patrice Chotard2a52a952017-09-27 15:44:48 +020063#define USART_CR3_OVRDIS BIT(12)
Vikas Manocha6c0c3ce2017-05-28 12:55:12 -070064
Patrice Chotard2a52a952017-09-27 15:44:48 +020065#define USART_SR_FLAG_RXNE BIT(5)
66#define USART_SR_FLAG_TXE BIT(7)
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080067
Patrice Chotard2a52a952017-09-27 15:44:48 +020068#define USART_BRR_F_MASK GENMASK(7, 0)
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080069#define USART_BRR_M_SHIFT 4
Patrice Chotard2a52a952017-09-27 15:44:48 +020070#define USART_BRR_M_MASK GENMASK(15, 4)
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080071
72#endif