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Simon Glass76565822019-12-06 21:42:58 -07001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Special driver to handle of-platdata
4 *
5 * Copyright 2019 Google LLC
6 *
7 * Some code from coreboot lpss.c
8 */
9
10#include <common.h>
11#include <dm.h>
12#include <dt-structs.h>
Simon Glass336d4612020-02-03 07:36:16 -070013#include <malloc.h>
Simon Glass76565822019-12-06 21:42:58 -070014#include <ns16550.h>
15#include <spl.h>
16#include <asm/io.h>
17#include <asm/pci.h>
18#include <asm/lpss.h>
19
20/* Low-power Subsystem (LPSS) clock register */
21enum {
22 LPSS_CLOCK_CTL_REG = 0x200,
23 LPSS_CNT_CLOCK_EN = 1,
24 LPSS_CNT_CLK_UPDATE = 1U << 31,
25 LPSS_CLOCK_DIV_N_SHIFT = 16,
26 LPSS_CLOCK_DIV_N_MASK = 0x7fff << LPSS_CLOCK_DIV_N_SHIFT,
27 LPSS_CLOCK_DIV_M_SHIFT = 1,
28 LPSS_CLOCK_DIV_M_MASK = 0x7fff << LPSS_CLOCK_DIV_M_SHIFT,
29
30 /* These set the UART input clock speed */
31 LPSS_UART_CLK_M_VAL = 0x25a,
32 LPSS_UART_CLK_N_VAL = 0x7fff,
33};
34
35static void lpss_clk_update(void *regs, u32 clk_m_val, u32 clk_n_val)
36{
37 u32 clk_sel;
38
39 clk_sel = clk_n_val << LPSS_CLOCK_DIV_N_SHIFT |
40 clk_m_val << LPSS_CLOCK_DIV_M_SHIFT;
41 clk_sel |= LPSS_CNT_CLK_UPDATE | LPSS_CNT_CLOCK_EN;
42
43 writel(clk_sel, regs + LPSS_CLOCK_CTL_REG);
44}
45
46static void uart_lpss_init(void *regs)
47{
48 /* Take UART out of reset */
49 lpss_reset_release(regs);
50
51 /* Set M and N divisor inputs and enable clock */
52 lpss_clk_update(regs, LPSS_UART_CLK_M_VAL, LPSS_UART_CLK_N_VAL);
53}
54
55void apl_uart_init(pci_dev_t bdf, ulong base)
56{
57 /* Set UART base address */
58 pci_x86_write_config(bdf, PCI_BASE_ADDRESS_0, base, PCI_SIZE_32);
59
60 /* Enable memory access and bus master */
61 pci_x86_write_config(bdf, PCI_COMMAND, PCI_COMMAND_MEMORY |
62 PCI_COMMAND_MASTER, PCI_SIZE_32);
63
64 uart_lpss_init((void *)base);
65}
66
67/*
68 * This driver uses its own compatible string but almost everything else from
69 * the standard ns16550 driver. This allows us to provide an of-platdata
70 * implementation, since the platdata produced by of-platdata does not match
Simon Glass8a8d24b2020-12-03 16:55:23 -070071 * struct ns16550_plat.
Simon Glass76565822019-12-06 21:42:58 -070072 *
73 * When running with of-platdata (generally TPL), the platdata is converted to
74 * something that ns16550 expects. When running withoutof-platdata (SPL, U-Boot
Simon Glassd1998a92020-12-03 16:55:21 -070075 * proper), we use ns16550's of_to_plat routine.
Simon Glass76565822019-12-06 21:42:58 -070076 */
77
78static int apl_ns16550_probe(struct udevice *dev)
79{
Simon Glass8a8d24b2020-12-03 16:55:23 -070080 struct ns16550_plat *plat = dev_get_plat(dev);
Simon Glass76565822019-12-06 21:42:58 -070081
82 if (!CONFIG_IS_ENABLED(PCI))
83 apl_uart_init(plat->bdf, plat->base);
84
85 return ns16550_serial_probe(dev);
86}
87
Simon Glassd1998a92020-12-03 16:55:21 -070088static int apl_ns16550_of_to_plat(struct udevice *dev)
Simon Glass76565822019-12-06 21:42:58 -070089{
90#if CONFIG_IS_ENABLED(OF_PLATDATA)
Simon Glassc69cda22020-12-03 16:55:20 -070091 struct dtd_intel_apl_ns16550 *dtplat = dev_get_plat(dev);
Simon Glass8a8d24b2020-12-03 16:55:23 -070092 struct ns16550_plat *plat;
Simon Glass76565822019-12-06 21:42:58 -070093
94 /*
Simon Glasscaa4daa2020-12-03 16:55:18 -070095 * Convert our plat to the ns16550's plat, so we can just use
Simon Glass76565822019-12-06 21:42:58 -070096 * that driver
97 */
98 plat = malloc(sizeof(*plat));
99 if (!plat)
100 return -ENOMEM;
101 plat->base = dtplat->early_regs[0];
102 plat->reg_width = 1;
103 plat->reg_shift = dtplat->reg_shift;
104 plat->reg_offset = 0;
105 plat->clock = dtplat->clock_frequency;
106 plat->fcr = UART_FCR_DEFVAL;
107 plat->bdf = pci_ofplat_get_devfn(dtplat->reg[0]);
Simon Glasscaa4daa2020-12-03 16:55:18 -0700108 dev->plat = plat;
Simon Glass76565822019-12-06 21:42:58 -0700109#else
110 int ret;
111
Simon Glassd1998a92020-12-03 16:55:21 -0700112 ret = ns16550_serial_of_to_plat(dev);
Simon Glass76565822019-12-06 21:42:58 -0700113 if (ret)
114 return ret;
115#endif /* OF_PLATDATA */
116
117 return 0;
118}
119
120static const struct udevice_id apl_ns16550_serial_ids[] = {
121 { .compatible = "intel,apl-ns16550" },
122 { },
123};
124
Simon Glass9d20db02020-10-05 05:27:01 -0600125U_BOOT_DRIVER(intel_apl_ns16550) = {
Simon Glass76565822019-12-06 21:42:58 -0700126 .name = "intel_apl_ns16550",
127 .id = UCLASS_SERIAL,
128 .of_match = apl_ns16550_serial_ids,
Simon Glass8a8d24b2020-12-03 16:55:23 -0700129 .plat_auto = sizeof(struct ns16550_plat),
Simon Glass41575d82020-12-03 16:55:17 -0700130 .priv_auto = sizeof(struct NS16550),
Simon Glass76565822019-12-06 21:42:58 -0700131 .ops = &ns16550_serial_ops,
Simon Glassd1998a92020-12-03 16:55:21 -0700132 .of_to_plat = apl_ns16550_of_to_plat,
Simon Glass76565822019-12-06 21:42:58 -0700133 .probe = apl_ns16550_probe,
134};