Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 2 | /* |
| 3 | * spi driver for rockchip |
| 4 | * |
| 5 | * (C) Copyright 2015 Google, Inc |
| 6 | * |
| 7 | * (C) Copyright 2008-2013 Rockchip Electronics |
| 8 | * Peter, Software Engineering, <superpeter.cai@gmail.com>. |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 9 | */ |
| 10 | |
| 11 | #include <common.h> |
| 12 | #include <clk.h> |
| 13 | #include <dm.h> |
Simon Glass | 6e019c4 | 2016-11-13 14:22:02 -0700 | [diff] [blame] | 14 | #include <dt-structs.h> |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 15 | #include <errno.h> |
| 16 | #include <spi.h> |
Masahiro Yamada | 1221ce4 | 2016-09-21 11:28:55 +0900 | [diff] [blame] | 17 | #include <linux/errno.h> |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 18 | #include <asm/io.h> |
| 19 | #include <asm/arch/clock.h> |
| 20 | #include <asm/arch/periph.h> |
| 21 | #include <dm/pinctrl.h> |
| 22 | #include "rk_spi.h" |
| 23 | |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 24 | /* Change to 1 to output registers at the start of each transaction */ |
| 25 | #define DEBUG_RK_SPI 0 |
| 26 | |
| 27 | struct rockchip_spi_platdata { |
Simon Glass | 6e019c4 | 2016-11-13 14:22:02 -0700 | [diff] [blame] | 28 | #if CONFIG_IS_ENABLED(OF_PLATDATA) |
| 29 | struct dtd_rockchip_rk3288_spi of_plat; |
| 30 | #endif |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 31 | s32 frequency; /* Default clock frequency, -1 for none */ |
| 32 | fdt_addr_t base; |
| 33 | uint deactivate_delay_us; /* Delay to wait after deactivate */ |
Simon Glass | 183a3a0 | 2016-01-21 19:44:10 -0700 | [diff] [blame] | 34 | uint activate_delay_us; /* Delay to wait after activate */ |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 35 | }; |
| 36 | |
| 37 | struct rockchip_spi_priv { |
| 38 | struct rockchip_spi *regs; |
Stephen Warren | 135aa95 | 2016-06-17 09:44:00 -0600 | [diff] [blame] | 39 | struct clk clk; |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 40 | unsigned int max_freq; |
| 41 | unsigned int mode; |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 42 | ulong last_transaction_us; /* Time of last transaction end */ |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 43 | unsigned int speed_hz; |
Simon Glass | 28a943c | 2016-01-21 19:44:03 -0700 | [diff] [blame] | 44 | unsigned int last_speed_hz; |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 45 | uint input_rate; |
| 46 | }; |
| 47 | |
| 48 | #define SPI_FIFO_DEPTH 32 |
| 49 | |
| 50 | static void rkspi_dump_regs(struct rockchip_spi *regs) |
| 51 | { |
| 52 | debug("ctrl0: \t\t0x%08x\n", readl(®s->ctrlr0)); |
| 53 | debug("ctrl1: \t\t0x%08x\n", readl(®s->ctrlr1)); |
| 54 | debug("ssienr: \t\t0x%08x\n", readl(®s->enr)); |
| 55 | debug("ser: \t\t0x%08x\n", readl(®s->ser)); |
| 56 | debug("baudr: \t\t0x%08x\n", readl(®s->baudr)); |
| 57 | debug("txftlr: \t\t0x%08x\n", readl(®s->txftlr)); |
| 58 | debug("rxftlr: \t\t0x%08x\n", readl(®s->rxftlr)); |
| 59 | debug("txflr: \t\t0x%08x\n", readl(®s->txflr)); |
| 60 | debug("rxflr: \t\t0x%08x\n", readl(®s->rxflr)); |
| 61 | debug("sr: \t\t0x%08x\n", readl(®s->sr)); |
| 62 | debug("imr: \t\t0x%08x\n", readl(®s->imr)); |
| 63 | debug("isr: \t\t0x%08x\n", readl(®s->isr)); |
| 64 | debug("dmacr: \t\t0x%08x\n", readl(®s->dmacr)); |
| 65 | debug("dmatdlr: \t0x%08x\n", readl(®s->dmatdlr)); |
| 66 | debug("dmardlr: \t0x%08x\n", readl(®s->dmardlr)); |
| 67 | } |
| 68 | |
| 69 | static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable) |
| 70 | { |
| 71 | writel(enable ? 1 : 0, ®s->enr); |
| 72 | } |
| 73 | |
| 74 | static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed) |
| 75 | { |
Philipp Tomsich | 9fc354e | 2017-04-20 22:05:52 +0200 | [diff] [blame] | 76 | /* |
| 77 | * We should try not to exceed the speed requested by the caller: |
| 78 | * when selecting a divider, we need to make sure we round up. |
| 79 | */ |
| 80 | uint clk_div = DIV_ROUND_UP(priv->input_rate, speed); |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 81 | |
Philipp Tomsich | 9fc354e | 2017-04-20 22:05:52 +0200 | [diff] [blame] | 82 | /* The baudrate register (BAUDR) is defined as a 32bit register where |
| 83 | * the upper 16bit are reserved and having 'Fsclk_out' in the lower |
| 84 | * 16bits with 'Fsclk_out' defined as follows: |
| 85 | * |
| 86 | * Fsclk_out = Fspi_clk/ SCKDV |
| 87 | * Where SCKDV is any even value between 2 and 65534. |
| 88 | */ |
| 89 | if (clk_div > 0xfffe) { |
| 90 | clk_div = 0xfffe; |
Heinrich Schuchardt | 11f12c1 | 2017-11-12 20:59:44 +0100 | [diff] [blame] | 91 | debug("%s: can't divide down to %d Hz (actual will be %d Hz)\n", |
Philipp Tomsich | 9fc354e | 2017-04-20 22:05:52 +0200 | [diff] [blame] | 92 | __func__, speed, priv->input_rate / clk_div); |
| 93 | } |
| 94 | |
| 95 | /* Round up to the next even 16bit number */ |
| 96 | clk_div = (clk_div + 1) & 0xfffe; |
| 97 | |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 98 | debug("spi speed %u, div %u\n", speed, clk_div); |
| 99 | |
Philipp Tomsich | 9fc354e | 2017-04-20 22:05:52 +0200 | [diff] [blame] | 100 | clrsetbits_le32(&priv->regs->baudr, 0xffff, clk_div); |
Simon Glass | 28a943c | 2016-01-21 19:44:03 -0700 | [diff] [blame] | 101 | priv->last_speed_hz = speed; |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 102 | } |
| 103 | |
| 104 | static int rkspi_wait_till_not_busy(struct rockchip_spi *regs) |
| 105 | { |
| 106 | unsigned long start; |
| 107 | |
| 108 | start = get_timer(0); |
| 109 | while (readl(®s->sr) & SR_BUSY) { |
| 110 | if (get_timer(start) > ROCKCHIP_SPI_TIMEOUT_MS) { |
| 111 | debug("RK SPI: Status keeps busy for 1000us after a read/write!\n"); |
| 112 | return -ETIMEDOUT; |
| 113 | } |
| 114 | } |
| 115 | |
| 116 | return 0; |
| 117 | } |
| 118 | |
Simon Glass | 183a3a0 | 2016-01-21 19:44:10 -0700 | [diff] [blame] | 119 | static void spi_cs_activate(struct udevice *dev, uint cs) |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 120 | { |
Simon Glass | 183a3a0 | 2016-01-21 19:44:10 -0700 | [diff] [blame] | 121 | struct udevice *bus = dev->parent; |
| 122 | struct rockchip_spi_platdata *plat = bus->platdata; |
| 123 | struct rockchip_spi_priv *priv = dev_get_priv(bus); |
| 124 | struct rockchip_spi *regs = priv->regs; |
| 125 | |
Simon Glass | b425247 | 2016-11-13 14:22:03 -0700 | [diff] [blame] | 126 | /* If it's too soon to do another transaction, wait */ |
| 127 | if (plat->deactivate_delay_us && priv->last_transaction_us) { |
| 128 | ulong delay_us; /* The delay completed so far */ |
| 129 | delay_us = timer_get_us() - priv->last_transaction_us; |
Philipp Tomsich | f92cf0a | 2019-02-03 16:17:26 +0100 | [diff] [blame] | 130 | if (delay_us < plat->deactivate_delay_us) { |
| 131 | ulong additional_delay_us = |
| 132 | plat->deactivate_delay_us - delay_us; |
| 133 | debug("%s: delaying by %ld us\n", |
| 134 | __func__, additional_delay_us); |
| 135 | udelay(additional_delay_us); |
| 136 | } |
Simon Glass | b425247 | 2016-11-13 14:22:03 -0700 | [diff] [blame] | 137 | } |
| 138 | |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 139 | debug("activate cs%u\n", cs); |
| 140 | writel(1 << cs, ®s->ser); |
Simon Glass | 183a3a0 | 2016-01-21 19:44:10 -0700 | [diff] [blame] | 141 | if (plat->activate_delay_us) |
| 142 | udelay(plat->activate_delay_us); |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 143 | } |
| 144 | |
Simon Glass | 183a3a0 | 2016-01-21 19:44:10 -0700 | [diff] [blame] | 145 | static void spi_cs_deactivate(struct udevice *dev, uint cs) |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 146 | { |
Simon Glass | 183a3a0 | 2016-01-21 19:44:10 -0700 | [diff] [blame] | 147 | struct udevice *bus = dev->parent; |
| 148 | struct rockchip_spi_platdata *plat = bus->platdata; |
| 149 | struct rockchip_spi_priv *priv = dev_get_priv(bus); |
| 150 | struct rockchip_spi *regs = priv->regs; |
| 151 | |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 152 | debug("deactivate cs%u\n", cs); |
| 153 | writel(0, ®s->ser); |
Simon Glass | 183a3a0 | 2016-01-21 19:44:10 -0700 | [diff] [blame] | 154 | |
| 155 | /* Remember time of this transaction so we can honour the bus delay */ |
| 156 | if (plat->deactivate_delay_us) |
| 157 | priv->last_transaction_us = timer_get_us(); |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 158 | } |
| 159 | |
Simon Glass | 6e019c4 | 2016-11-13 14:22:02 -0700 | [diff] [blame] | 160 | #if CONFIG_IS_ENABLED(OF_PLATDATA) |
| 161 | static int conv_of_platdata(struct udevice *dev) |
| 162 | { |
| 163 | struct rockchip_spi_platdata *plat = dev->platdata; |
| 164 | struct dtd_rockchip_rk3288_spi *dtplat = &plat->of_plat; |
| 165 | struct rockchip_spi_priv *priv = dev_get_priv(dev); |
| 166 | int ret; |
| 167 | |
| 168 | plat->base = dtplat->reg[0]; |
| 169 | plat->frequency = 20000000; |
| 170 | ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk); |
| 171 | if (ret < 0) |
| 172 | return ret; |
| 173 | dev->req_seq = 0; |
| 174 | |
| 175 | return 0; |
| 176 | } |
| 177 | #endif |
| 178 | |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 179 | static int rockchip_spi_ofdata_to_platdata(struct udevice *bus) |
| 180 | { |
Simon Glass | 6e019c4 | 2016-11-13 14:22:02 -0700 | [diff] [blame] | 181 | #if !CONFIG_IS_ENABLED(OF_PLATDATA) |
| 182 | struct rockchip_spi_platdata *plat = dev_get_platdata(bus); |
Simon Glass | 71037d1 | 2016-01-21 19:43:43 -0700 | [diff] [blame] | 183 | struct rockchip_spi_priv *priv = dev_get_priv(bus); |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 184 | int ret; |
| 185 | |
Philipp Tomsich | d27c273 | 2017-09-11 22:04:20 +0200 | [diff] [blame] | 186 | plat->base = dev_read_addr(bus); |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 187 | |
Simon Glass | 71037d1 | 2016-01-21 19:43:43 -0700 | [diff] [blame] | 188 | ret = clk_get_by_index(bus, 0, &priv->clk); |
| 189 | if (ret < 0) { |
| 190 | debug("%s: Could not get clock for %s: %d\n", __func__, |
| 191 | bus->name, ret); |
| 192 | return ret; |
| 193 | } |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 194 | |
Philipp Tomsich | 6c65577c | 2017-06-07 18:45:58 +0200 | [diff] [blame] | 195 | plat->frequency = |
| 196 | dev_read_u32_default(bus, "spi-max-frequency", 50000000); |
| 197 | plat->deactivate_delay_us = |
| 198 | dev_read_u32_default(bus, "spi-deactivate-delay", 0); |
| 199 | plat->activate_delay_us = |
| 200 | dev_read_u32_default(bus, "spi-activate-delay", 0); |
| 201 | |
Simon Glass | 90a2847 | 2016-01-21 19:44:12 -0700 | [diff] [blame] | 202 | debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n", |
| 203 | __func__, (uint)plat->base, plat->frequency, |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 204 | plat->deactivate_delay_us); |
Simon Glass | 6e019c4 | 2016-11-13 14:22:02 -0700 | [diff] [blame] | 205 | #endif |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 206 | |
| 207 | return 0; |
| 208 | } |
| 209 | |
Philipp Tomsich | bd37671 | 2017-04-20 22:05:51 +0200 | [diff] [blame] | 210 | static int rockchip_spi_calc_modclk(ulong max_freq) |
| 211 | { |
Philipp Tomsich | d16120a | 2017-07-25 16:25:30 +0200 | [diff] [blame] | 212 | /* |
| 213 | * While this is not strictly correct for the RK3368, as the |
| 214 | * GPLL will be 576MHz, things will still work, as the |
| 215 | * clk_set_rate(...) implementation in our clock-driver will |
| 216 | * chose the next closest rate not exceeding what we request |
| 217 | * based on the output of this function. |
| 218 | */ |
| 219 | |
Philipp Tomsich | bd37671 | 2017-04-20 22:05:51 +0200 | [diff] [blame] | 220 | unsigned div; |
| 221 | const unsigned long gpll_hz = 594000000UL; |
| 222 | |
| 223 | /* |
| 224 | * We need to find an input clock that provides at least twice |
| 225 | * the maximum frequency and can be generated from the assumed |
| 226 | * speed of GPLL (594MHz) using an integer divider. |
| 227 | * |
| 228 | * To give us more achievable bitrates at higher speeds (these |
| 229 | * are generated by dividing by an even 16-bit integer from |
| 230 | * this frequency), we try to have an input frequency of at |
| 231 | * least 4x our max_freq. |
| 232 | */ |
| 233 | |
| 234 | div = DIV_ROUND_UP(gpll_hz, max_freq * 4); |
| 235 | return gpll_hz / div; |
| 236 | } |
| 237 | |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 238 | static int rockchip_spi_probe(struct udevice *bus) |
| 239 | { |
| 240 | struct rockchip_spi_platdata *plat = dev_get_platdata(bus); |
| 241 | struct rockchip_spi_priv *priv = dev_get_priv(bus); |
| 242 | int ret; |
| 243 | |
| 244 | debug("%s: probe\n", __func__); |
Simon Glass | 6e019c4 | 2016-11-13 14:22:02 -0700 | [diff] [blame] | 245 | #if CONFIG_IS_ENABLED(OF_PLATDATA) |
| 246 | ret = conv_of_platdata(bus); |
| 247 | if (ret) |
| 248 | return ret; |
| 249 | #endif |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 250 | priv->regs = (struct rockchip_spi *)plat->base; |
| 251 | |
| 252 | priv->last_transaction_us = timer_get_us(); |
| 253 | priv->max_freq = plat->frequency; |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 254 | |
Philipp Tomsich | bd37671 | 2017-04-20 22:05:51 +0200 | [diff] [blame] | 255 | /* Clamp the value from the DTS against any hardware limits */ |
| 256 | if (priv->max_freq > ROCKCHIP_SPI_MAX_RATE) |
| 257 | priv->max_freq = ROCKCHIP_SPI_MAX_RATE; |
| 258 | |
| 259 | /* Find a module-input clock that fits with the max_freq setting */ |
| 260 | ret = clk_set_rate(&priv->clk, |
| 261 | rockchip_spi_calc_modclk(priv->max_freq)); |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 262 | if (ret < 0) { |
| 263 | debug("%s: Failed to set clock: %d\n", __func__, ret); |
| 264 | return ret; |
| 265 | } |
| 266 | priv->input_rate = ret; |
| 267 | debug("%s: rate = %u\n", __func__, priv->input_rate); |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 268 | |
| 269 | return 0; |
| 270 | } |
| 271 | |
| 272 | static int rockchip_spi_claim_bus(struct udevice *dev) |
| 273 | { |
| 274 | struct udevice *bus = dev->parent; |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 275 | struct rockchip_spi_priv *priv = dev_get_priv(bus); |
| 276 | struct rockchip_spi *regs = priv->regs; |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 277 | uint ctrlr0; |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 278 | |
| 279 | /* Disable the SPI hardware */ |
Philipp Tomsich | b6101e9 | 2019-02-03 16:17:29 +0100 | [diff] [blame] | 280 | rkspi_enable_chip(regs, false); |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 281 | |
Simon Glass | 28a943c | 2016-01-21 19:44:03 -0700 | [diff] [blame] | 282 | if (priv->speed_hz != priv->last_speed_hz) |
| 283 | rkspi_set_clk(priv, priv->speed_hz); |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 284 | |
| 285 | /* Operation Mode */ |
| 286 | ctrlr0 = OMOD_MASTER << OMOD_SHIFT; |
| 287 | |
| 288 | /* Data Frame Size */ |
Philipp Tomsich | 0e661b6 | 2019-02-03 16:17:27 +0100 | [diff] [blame] | 289 | ctrlr0 |= DFS_8BIT << DFS_SHIFT; |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 290 | |
| 291 | /* set SPI mode 0..3 */ |
| 292 | if (priv->mode & SPI_CPOL) |
| 293 | ctrlr0 |= SCOL_HIGH << SCOL_SHIFT; |
| 294 | if (priv->mode & SPI_CPHA) |
| 295 | ctrlr0 |= SCPH_TOGSTA << SCPH_SHIFT; |
| 296 | |
| 297 | /* Chip Select Mode */ |
| 298 | ctrlr0 |= CSM_KEEP << CSM_SHIFT; |
| 299 | |
| 300 | /* SSN to Sclk_out delay */ |
| 301 | ctrlr0 |= SSN_DELAY_ONE << SSN_DELAY_SHIFT; |
| 302 | |
| 303 | /* Serial Endian Mode */ |
| 304 | ctrlr0 |= SEM_LITTLE << SEM_SHIFT; |
| 305 | |
| 306 | /* First Bit Mode */ |
| 307 | ctrlr0 |= FBM_MSB << FBM_SHIFT; |
| 308 | |
| 309 | /* Byte and Halfword Transform */ |
Philipp Tomsich | 0e661b6 | 2019-02-03 16:17:27 +0100 | [diff] [blame] | 310 | ctrlr0 |= HALF_WORD_OFF << HALF_WORD_TX_SHIFT; |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 311 | |
| 312 | /* Rxd Sample Delay */ |
| 313 | ctrlr0 |= 0 << RXDSD_SHIFT; |
| 314 | |
| 315 | /* Frame Format */ |
| 316 | ctrlr0 |= FRF_SPI << FRF_SHIFT; |
| 317 | |
| 318 | /* Tx and Rx mode */ |
Philipp Tomsich | 0e661b6 | 2019-02-03 16:17:27 +0100 | [diff] [blame] | 319 | ctrlr0 |= TMOD_TR << TMOD_SHIFT; |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 320 | |
| 321 | writel(ctrlr0, ®s->ctrlr0); |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 322 | |
| 323 | return 0; |
| 324 | } |
| 325 | |
| 326 | static int rockchip_spi_release_bus(struct udevice *dev) |
| 327 | { |
Simon Glass | e15af8e | 2016-01-21 19:44:11 -0700 | [diff] [blame] | 328 | struct udevice *bus = dev->parent; |
| 329 | struct rockchip_spi_priv *priv = dev_get_priv(bus); |
| 330 | |
| 331 | rkspi_enable_chip(priv->regs, false); |
| 332 | |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 333 | return 0; |
| 334 | } |
| 335 | |
| 336 | static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen, |
| 337 | const void *dout, void *din, unsigned long flags) |
| 338 | { |
| 339 | struct udevice *bus = dev->parent; |
| 340 | struct rockchip_spi_priv *priv = dev_get_priv(bus); |
| 341 | struct rockchip_spi *regs = priv->regs; |
| 342 | struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); |
| 343 | int len = bitlen >> 3; |
| 344 | const u8 *out = dout; |
| 345 | u8 *in = din; |
| 346 | int toread, towrite; |
| 347 | int ret; |
| 348 | |
| 349 | debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din, |
| 350 | len, flags); |
| 351 | if (DEBUG_RK_SPI) |
| 352 | rkspi_dump_regs(regs); |
| 353 | |
| 354 | /* Assert CS before transfer */ |
| 355 | if (flags & SPI_XFER_BEGIN) |
Simon Glass | 183a3a0 | 2016-01-21 19:44:10 -0700 | [diff] [blame] | 356 | spi_cs_activate(dev, slave_plat->cs); |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 357 | |
| 358 | while (len > 0) { |
Philipp Tomsich | e647dec | 2019-02-03 16:17:28 +0100 | [diff] [blame] | 359 | int todo = min(len, 0x10000); |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 360 | |
Simon Glass | e15af8e | 2016-01-21 19:44:11 -0700 | [diff] [blame] | 361 | rkspi_enable_chip(regs, false); |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 362 | writel(todo - 1, ®s->ctrlr1); |
| 363 | rkspi_enable_chip(regs, true); |
| 364 | |
| 365 | toread = todo; |
| 366 | towrite = todo; |
| 367 | while (toread || towrite) { |
| 368 | u32 status = readl(®s->sr); |
| 369 | |
| 370 | if (towrite && !(status & SR_TF_FULL)) { |
| 371 | writel(out ? *out++ : 0, regs->txdr); |
| 372 | towrite--; |
| 373 | } |
| 374 | if (toread && !(status & SR_RF_EMPT)) { |
| 375 | u32 byte = readl(regs->rxdr); |
| 376 | |
| 377 | if (in) |
| 378 | *in++ = byte; |
| 379 | toread--; |
| 380 | } |
| 381 | } |
Philipp Tomsich | 7e0e5c5 | 2019-02-03 16:17:30 +0100 | [diff] [blame^] | 382 | |
| 383 | /* |
| 384 | * In case that there's a transmit-component, we need to wait |
| 385 | * until the control goes idle before we can disable the SPI |
| 386 | * control logic (as this will implictly flush the FIFOs). |
| 387 | */ |
| 388 | if (out) { |
| 389 | ret = rkspi_wait_till_not_busy(regs); |
| 390 | if (ret) |
| 391 | break; |
| 392 | } |
| 393 | |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 394 | len -= todo; |
| 395 | } |
| 396 | |
| 397 | /* Deassert CS after transfer */ |
| 398 | if (flags & SPI_XFER_END) |
Simon Glass | 183a3a0 | 2016-01-21 19:44:10 -0700 | [diff] [blame] | 399 | spi_cs_deactivate(dev, slave_plat->cs); |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 400 | |
| 401 | rkspi_enable_chip(regs, false); |
| 402 | |
| 403 | return ret; |
| 404 | } |
| 405 | |
| 406 | static int rockchip_spi_set_speed(struct udevice *bus, uint speed) |
| 407 | { |
| 408 | struct rockchip_spi_priv *priv = dev_get_priv(bus); |
| 409 | |
Philipp Tomsich | bd37671 | 2017-04-20 22:05:51 +0200 | [diff] [blame] | 410 | /* Clamp to the maximum frequency specified in the DTS */ |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 411 | if (speed > priv->max_freq) |
| 412 | speed = priv->max_freq; |
Philipp Tomsich | bd37671 | 2017-04-20 22:05:51 +0200 | [diff] [blame] | 413 | |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 414 | priv->speed_hz = speed; |
| 415 | |
| 416 | return 0; |
| 417 | } |
| 418 | |
| 419 | static int rockchip_spi_set_mode(struct udevice *bus, uint mode) |
| 420 | { |
| 421 | struct rockchip_spi_priv *priv = dev_get_priv(bus); |
| 422 | |
| 423 | priv->mode = mode; |
| 424 | |
| 425 | return 0; |
| 426 | } |
| 427 | |
| 428 | static const struct dm_spi_ops rockchip_spi_ops = { |
| 429 | .claim_bus = rockchip_spi_claim_bus, |
| 430 | .release_bus = rockchip_spi_release_bus, |
| 431 | .xfer = rockchip_spi_xfer, |
| 432 | .set_speed = rockchip_spi_set_speed, |
| 433 | .set_mode = rockchip_spi_set_mode, |
| 434 | /* |
| 435 | * cs_info is not needed, since we require all chip selects to be |
| 436 | * in the device tree explicitly |
| 437 | */ |
| 438 | }; |
| 439 | |
| 440 | static const struct udevice_id rockchip_spi_ids[] = { |
| 441 | { .compatible = "rockchip,rk3288-spi" }, |
Philipp Tomsich | d16120a | 2017-07-25 16:25:30 +0200 | [diff] [blame] | 442 | { .compatible = "rockchip,rk3368-spi" }, |
Jakob Unterwurzacher | cdeb4d7 | 2017-04-20 22:05:54 +0200 | [diff] [blame] | 443 | { .compatible = "rockchip,rk3399-spi" }, |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 444 | { } |
| 445 | }; |
| 446 | |
| 447 | U_BOOT_DRIVER(rockchip_spi) = { |
Simon Glass | 6e019c4 | 2016-11-13 14:22:02 -0700 | [diff] [blame] | 448 | #if CONFIG_IS_ENABLED(OF_PLATDATA) |
| 449 | .name = "rockchip_rk3288_spi", |
| 450 | #else |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 451 | .name = "rockchip_spi", |
Simon Glass | 6e019c4 | 2016-11-13 14:22:02 -0700 | [diff] [blame] | 452 | #endif |
Simon Glass | 1b2fd5b | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 453 | .id = UCLASS_SPI, |
| 454 | .of_match = rockchip_spi_ids, |
| 455 | .ops = &rockchip_spi_ops, |
| 456 | .ofdata_to_platdata = rockchip_spi_ofdata_to_platdata, |
| 457 | .platdata_auto_alloc_size = sizeof(struct rockchip_spi_platdata), |
| 458 | .priv_auto_alloc_size = sizeof(struct rockchip_spi_priv), |
| 459 | .probe = rockchip_spi_probe, |
| 460 | }; |