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TsiChungLiewaa5f1f92008-01-14 17:23:08 -06001/*
2 * Configuation settings for the Freescale MCF5373 FireEngine board.
3 *
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26/*
27 * board/config.h - configuration options, board specific
28 */
29
30#ifndef _M5373EVB_H
31#define _M5373EVB_H
32
33/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37#define CONFIG_MCF532x /* define processor family */
38#define CONFIG_M5373 /* define processor type */
39
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060040#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041#define CONFIG_SYS_UART_PORT (0)
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060042#define CONFIG_BAUDRATE 115200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020043#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060044
45#undef CONFIG_WATCHDOG
46#define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */
47
48/* Command line configuration */
49#include <config_cmd_default.h>
50
51#define CONFIG_CMD_CACHE
52#define CONFIG_CMD_DATE
53#define CONFIG_CMD_ELF
54#define CONFIG_CMD_FLASH
55#define CONFIG_CMD_I2C
56#define CONFIG_CMD_MEMORY
57#define CONFIG_CMD_MISC
58#define CONFIG_CMD_MII
59#define CONFIG_CMD_NET
60#define CONFIG_CMD_PING
61#define CONFIG_CMD_REGINFO
62
63#ifdef NANDFLASH_SIZE
64# define CONFIG_CMD_NAND
65#endif
66
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067#define CONFIG_SYS_UNIFY_CACHE
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060068
69#define CONFIG_MCFFEC
70#ifdef CONFIG_MCFFEC
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060071# define CONFIG_MII 1
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -050072# define CONFIG_MII_INIT 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073# define CONFIG_SYS_DISCOVER_PHY
74# define CONFIG_SYS_RX_ETH_BUFFER 8
75# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060076
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077# define CONFIG_SYS_FEC0_PINMUX 0
78# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
Wolfgang Denk53677ef2008-05-20 16:00:29 +020079# define MCFFEC_TOUT_LOOP 50000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
81# ifndef CONFIG_SYS_DISCOVER_PHY
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060082# define FECDUPLEX FULL
83# define FECSPEED _100BASET
84# else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
86# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060087# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088# endif /* CONFIG_SYS_DISCOVER_PHY */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060089#endif
90
91#define CONFIG_MCFRTC
92#undef RTC_DEBUG
93
94/* Timer */
95#define CONFIG_MCFTMR
96#undef CONFIG_MCFPIT
97
98/* I2C */
99#define CONFIG_FSL_I2C
100#define CONFIG_HARD_I2C /* I2C with hw support */
101#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_I2C_SPEED 80000
103#define CONFIG_SYS_I2C_SLAVE 0x7F
104#define CONFIG_SYS_I2C_OFFSET 0x58000
105#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600106
107#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
108#define CONFIG_UDP_CHECKSUM
109
110#ifdef CONFIG_MCFFEC
111# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
112# define CONFIG_IPADDR 192.162.1.2
113# define CONFIG_NETMASK 255.255.255.0
114# define CONFIG_SERVERIP 192.162.1.1
115# define CONFIG_GATEWAYIP 192.162.1.1
116# define CONFIG_OVERWRITE_ETHADDR_ONCE
117#endif /* FEC_ENET */
118
119#define CONFIG_HOSTNAME M5373EVB
120#define CONFIG_EXTRA_ENV_SETTINGS \
121 "netdev=eth0\0" \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122 "loadaddr=" MK_STR(CONFIG_SYS_LOAD_ADDR) "\0" \
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600123 "u-boot=u-boot.bin\0" \
124 "load=tftp ${loadaddr) ${u-boot}\0" \
125 "upd=run load; run prog\0" \
Jason Jin09933fb2011-08-19 10:10:40 +0800126 "prog=prot off 0 3ffff;" \
127 "era 0 3ffff;" \
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600128 "cp.b ${loadaddr} 0 ${filesize};" \
129 "save\0" \
130 ""
131
132#define CONFIG_PRAM 512 /* 512 KB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_PROMPT "-> "
134#define CONFIG_SYS_LONGHELP /* undef to save memory */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600135
136#ifdef CONFIG_CMD_KGDB
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600138#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600140#endif
141
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
143#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
144#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
145#define CONFIG_SYS_LOAD_ADDR 0x40010000
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600146
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_HZ 1000
148#define CONFIG_SYS_CLK 80000000
149#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600150
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_MBAR 0xFC000000
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600152
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600154
155/*
156 * Low Level Configuration Settings
157 * (address mappings, register initial values, etc.)
158 * You should know what you are doing if you make changes here.
159 */
160/*-----------------------------------------------------------------------
161 * Definitions for initial stack pointer and data area (in DPRAM)
162 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200164#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_INIT_RAM_CTRL 0x221
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200166#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600168
169/*-----------------------------------------------------------------------
170 * Start addresses for the final memory configuration
171 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600173 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_SDRAM_BASE 0x40000000
175#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
176#define CONFIG_SYS_SDRAM_CFG1 0x53722730
177#define CONFIG_SYS_SDRAM_CFG2 0x56670000
178#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
179#define CONFIG_SYS_SDRAM_EMOD 0x40010000
180#define CONFIG_SYS_SDRAM_MODE 0x018D0000
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600181
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
183#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600184
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
186#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600187
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
189#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600190
191/*
192 * For booting Linux, the board info and command line data
193 * have to be in the first 8 MB of memory, since this is
194 * the maximum mapped by the Linux kernel during initialization ??
195 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
TsiChung Liewd6e4baf2009-01-27 12:57:47 +0000197#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600198
199/*-----------------------------------------------------------------------
200 * FLASH organization
201 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_FLASH_CFI
203#ifdef CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200204# define CONFIG_FLASH_CFI_DRIVER 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
206# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
207# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
208# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
209# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600210#endif
211
212#ifdef NANDFLASH_SIZE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213# define CONFIG_SYS_MAX_NAND_DEVICE 1
214# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
215# define CONFIG_SYS_NAND_SIZE 1
216# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600217# define NAND_ALLOW_ERASE_ALL 1
218# define CONFIG_JFFS2_NAND 1
219# define CONFIG_JFFS2_DEV "nand0"
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220# define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1)
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600221# define CONFIG_JFFS2_PART_OFFSET 0x00000000
222#endif
223
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600225
226/* Configuration for environment
227 * Environment is embedded in u-boot in the second sector of the flash
228 */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200229#define CONFIG_ENV_OFFSET 0x4000
230#define CONFIG_ENV_SECT_SIZE 0x2000
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200231#define CONFIG_ENV_IS_IN_FLASH 1
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600232
233/*-----------------------------------------------------------------------
234 * Cache Configuration
235 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_CACHELINE_SIZE 16
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600237
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600238#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200239 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600240#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200241 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600242#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
243#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
244 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
245 CF_ACR_EN | CF_ACR_SM_ALL)
246#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
247 CF_CACR_DCM_P)
248
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600249/*-----------------------------------------------------------------------
250 * Chipselect bank definitions
251 */
252/*
253 * CS0 - NOR Flash 1, 2, 4, or 8MB
254 * CS1 - CompactFlash and registers
255 * CS2 - NAND Flash 16, 32, or 64MB
256 * CS3 - Available
257 * CS4 - Available
258 * CS5 - Available
259 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_CS0_BASE 0
261#define CONFIG_SYS_CS0_MASK 0x007f0001
262#define CONFIG_SYS_CS0_CTRL 0x00001fa0
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600263
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_CS1_BASE 0x10000000
265#define CONFIG_SYS_CS1_MASK 0x001f0001
266#define CONFIG_SYS_CS1_CTRL 0x002A3780
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600267
268#ifdef NANDFLASH_SIZE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_CS2_BASE 0x20000000
270#define CONFIG_SYS_CS2_MASK ((NANDFLASH_SIZE << 20) | 1)
271#define CONFIG_SYS_CS2_CTRL 0x00001f60
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600272#endif
273
274#endif /* _M5373EVB_H */