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Stephen Arnold8baa1782017-03-23 18:58:08 -07001----------------------------------------
Chin Liang Seec5c1af22013-12-30 18:26:14 -06002SOCFPGA Documentation for U-Boot and SPL
Stephen Arnold8baa1782017-03-23 18:58:08 -07003----------------------------------------
Chin Liang Seec5c1af22013-12-30 18:26:14 -06004
5This README is about U-Boot and SPL support for Altera's ARM Cortex-A9MPCore
6based SOCFPGA. To know more about the hardware itself, please refer to
7www.altera.com.
8
Dalon Westergreen5c0adb02019-09-27 18:43:24 -07009---------------------------------------------------------------------
10Cyclone 5 / Arria 5 generating the handoff header files for U-Boot SPL
11---------------------------------------------------------------------
Stephen Arnold8baa1782017-03-23 18:58:08 -070012
13This text is assuming quartus 16.1, but newer versions will probably work just fine too;
14verified with DE1_SOC_Linux_FB demo project (https://github.com/VCTLabs/DE1_SOC_Linux_FB).
15Updated/working projects should build using either process below.
16
17Note: it *should* work from Quartus 14.0.200 onwards, however, the current vendor demo
18projects must have the IP cores updated as shown below.
19
20Rebuilding your Quartus project
21-------------------------------
22
23Choose one of the follwing methods, either command line or GUI.
24
Dalon Westergreen5c0adb02019-09-27 18:43:24 -070025Using the command line
Stephen Arnold8baa1782017-03-23 18:58:08 -070026~~~~~~~~~~~~~~~~~~~~~~
27
28First run the embedded command shell, using your path to the Quartus install:
29
30 $ /path/to/intelFPGA/16.1/embedded/embedded_command_shell.sh
31
32Then (if necessary) update the IP cores in the project, generate HDL code, and
33build the project:
34
35 $ cd path/to/project/dir
36 $ qsys-generate soc_system.qsys --upgrade-ip-cores
37 $ qsys-generate soc_system.qsys --synthesis=[VERILOG|VHDL]
38 $ quartus_sh --flow compile <project name>
39
40Convert the resulting .sof file (SRAM object file) to .rbf file (Raw bit file):
41
42 $ quartus_cpf -c <project_name>.sof soc_system.rbf
43
44
45Generate BSP handoff files
46~~~~~~~~~~~~~~~~~~~~~~~~~~
47
48You can run the bsp editor GUI below, or run the following command from the
49project directory:
50
51 $ /path/to/bsb/tools/bsp-create-settings --type spl --bsp-dir build \
52 --preloader-settings-dir hps_isw_handoff/soc_system_hps_0/ \
53 --settings build/settings.bsp
54
55You should use the bsp "build" directory above (ie, where the settings.bsp file is)
56in the following u-boot command to update the board headers. Once these headers
57are updated for a given project build, u-boot should be configured for the
58project board (eg, de0-nano-sockit) and then build the normal spl build.
59
60Now you can skip the GUI section.
61
62
63Using the Qsys GUI
64~~~~~~~~~~~~~~~~~~
65
661. Navigate to your project directory
672. Run Quartus II
683. Open Project (Ctrl+J), select <project_name>.qpf
694. Run QSys [Tools->QSys]
70 4.1 In the Open dialog, select '<project_name>.qsys'
71 4.2 In the Open System dialog, wait until completion and press 'Close'
72 4.3 In the Qsys window, click on 'Generate HDL...' in bottom right corner
73 4.3.1 In the 'Generation' window, click 'Generate'
74 4.3.2 In the 'Generate' dialog, wait until completion and click 'Close'
75 4.4 In the QSys window, click 'Finish'
76 4.4.1 In the 'Quartus II' pop up window, click 'OK'
775. Back in Quartus II main window, do the following
78 5.1 Use Processing -> Start -> Start Analysis & Synthesis (Ctrl+K)
79 5.2 Use Processing -> Start Compilation (Ctrl+L)
80
81 ... this may take some time, have patience ...
82
836. Start the embedded command shell as shown in the previous section
84 6.1 Change directory to 'software/spl_bsp'
85 6.2 Prepare BSP by launching the BSP editor from ECS
86 => bsp-editor
87 6.3 In BSP editor
88 6.3.1 Use File -> Open
89 6.3.2 Select 'settings.bsp' file
90 6.3.3 Click Generate
91 6.3.4 Click Exit
92
93
94Post handoff generation
95~~~~~~~~~~~~~~~~~~~~~~~
96
97Now that the handoff files are generated, U-Boot can be used to process
98the handoff files generated by the bsp-editor. For this, please use the
99following script from the u-boot source tree:
100
101 $ ./arch/arm/mach-socfpga/qts-filter.sh \
102 <soc_type> \
103 <input_qts_dir> \
104 <input_bsp_dir> \
105 <output_dir>
106
107Process QTS-generated files into U-Boot compatible ones.
108
109 soc_type - Type of SoC, either 'cyclone5' or 'arria5'.
110 input_qts_dir - Directory with compiled Quartus project
111 and containing the Quartus project file (QPF).
112 input_bsp_dir - Directory with generated bsp containing
113 the settings.bsp file.
114 output_dir - Directory to store the U-Boot compatible
115 headers.
116
117This will generate (or update) the following 4 files:
118
119 iocsr_config.h
120 pinmux_config.h
121 pll_config.h
122 sdram_config.h
123
124These files should be copied into "qts" directory in the board directory
125(see output argument of qts-filter.sh command above).
126
127Here is an example for the DE-0 Nano SoC after the above rebuild process:
128
129 $ ll board/terasic/de0-nano-soc/qts/
130 total 36
131 -rw-r--r-- 1 sarnold sarnold 8826 Mar 21 18:11 iocsr_config.h
132 -rw-r--r-- 1 sarnold sarnold 4398 Mar 21 18:11 pinmux_config.h
133 -rw-r--r-- 1 sarnold sarnold 3190 Mar 21 18:11 pll_config.h
134 -rw-r--r-- 1 sarnold sarnold 9022 Mar 21 18:11 sdram_config.h
135
136Note: file sizes will differ slightly depending on the selected board.
137
138Now your board is ready for full mainline support including U-Boot SPL.
139The Preloader will not be needed any more.
Dalon Westergreen5c0adb02019-09-27 18:43:24 -0700140
141----------------------------------------------------------
142Arria 10 generating the handoff header files for U-Boot SPL
143----------------------------------------------------------
144
145A header file for inclusion in a devicetree for Arria10 can be generated
146by the qts-filter-a10.sh script directly from the hps_isw_handoff/hps.xml
147file generated during the FPGA project compilation. The header contains
148all PLL, clock, pinmux, and bridge configurations required.
149
150Please look at the socfpga_arria10_socdk_sdmmc-u-boot.dtsi for an example
151that includes use of the generated handoff header.
152
153Devicetree header generation
154~~~~~~~~~~~~~~~~~~~~~~~~~~~~
155
156The qts-filter-a10.sh script can process the compile time genetated hps.xml
157to create the appropriate devicetree header.
158
159
160 $ ./arch/arm/mach-socfpga/qts-filter-a10.sh \
161 <hps_xml> \
162 <output_file>
163
164 hps_xml - hps_isw_handoff/hps.xml from Quartus project
165 output_file - Output filename and location for header file
166
167The script generates a single header file names <output_file> that should
168be placed in arch/arm/dts.