| wdenk | 5c952cf | 2004-10-10 21:27:30 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2004, Psyent Corporation <www.psyent.com> |
| 3 | * Scott McNutt <smcnutt@psyent.com> |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #ifndef __CONFIG_H |
| 25 | #define __CONFIG_H |
| 26 | |
| 27 | /*------------------------------------------------------------------------ |
| 28 | * BOARD/CPU |
| 29 | *----------------------------------------------------------------------*/ |
| 30 | #define CONFIG_PK1C20 1 /* PK1C20 board */ |
| 31 | #define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */ |
| 32 | |
| 33 | #define CFG_RESET_ADDR 0x00000000 /* Hard-reset address */ |
| 34 | #define CFG_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/ |
| 35 | #define CFG_NIOS_SYSID_BASE 0x00920828 /* System id address */ |
| 36 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/ |
| 37 | |
| 38 | /*------------------------------------------------------------------------ |
| 39 | * CACHE -- the following will support II/s and II/f. The II/s does not |
| 40 | * have dcache, so the cache instructions will behave as NOPs. |
| 41 | *----------------------------------------------------------------------*/ |
| 42 | #define CFG_ICACHE_SIZE 4096 /* 4 KByte total */ |
| 43 | #define CFG_ICACHELINE_SIZE 32 /* 32 bytes/line */ |
| 44 | #define CFG_DCACHE_SIZE 2048 /* 2 KByte (II/f) */ |
| 45 | #define CFG_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */ |
| 46 | |
| 47 | /*------------------------------------------------------------------------ |
| 48 | * MEMORY BASE ADDRESSES |
| 49 | *----------------------------------------------------------------------*/ |
| 50 | #define CFG_FLASH_BASE 0x00000000 /* FLASH base addr */ |
| 51 | #define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */ |
| 52 | #define CFG_SDRAM_BASE 0x01000000 /* SDRAM base addr */ |
| 53 | #define CFG_SDRAM_SIZE 0x01000000 /* 16 MByte */ |
| 54 | #define CFG_SRAM_BASE 0x00800000 /* SRAM base addr */ |
| 55 | #define CFG_SRAM_SIZE 0x00200000 /* 2 MByte */ |
| 56 | |
| 57 | /*------------------------------------------------------------------------ |
| 58 | * MEMORY ORGANIZATION |
| 59 | * -Monitor at top. |
| 60 | * -The heap is placed below the monitor. |
| 61 | * -Global data is placed below the heap. |
| 62 | * -The stack is placed below global data (&grows down). |
| 63 | *----------------------------------------------------------------------*/ |
| 64 | #define CFG_MONITOR_LEN (128 * 1024) /* Reserve 128k */ |
| 65 | #define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/ |
| 66 | #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) |
| 67 | |
| 68 | #define CFG_MONITOR_BASE TEXT_BASE |
| 69 | #define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) |
| 70 | #define CFG_GBL_DATA_OFFSET (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) |
| 71 | #define CFG_INIT_SP CFG_GBL_DATA_OFFSET |
| 72 | |
| 73 | /*------------------------------------------------------------------------ |
| 74 | * FLASH (AM29LV065D) |
| 75 | *----------------------------------------------------------------------*/ |
| 76 | #define CFG_MAX_FLASH_SECT 128 /* Max # sects per bank */ |
| 77 | #define CFG_MAX_FLASH_BANKS 1 /* Max # of flash banks */ |
| 78 | #define CFG_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ |
| 79 | #define CFG_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ |
| 80 | #define CFG_FLASH_WORD_SIZE unsigned char /* flash word size */ |
| 81 | |
| 82 | /*------------------------------------------------------------------------ |
| 83 | * ENVIRONMENT -- Put environment in sector CFG_MONITOR_LEN above |
| 84 | * CFG_RESET_ADDR, since we assume the monitor is stored at the |
| 85 | * reset address, no? This will keep the environment in user region |
| 86 | * of flash. NOTE: the monitor length must be multiple of sector size |
| 87 | * (which is common practice). |
| 88 | *----------------------------------------------------------------------*/ |
| 89 | #define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */ |
| 90 | #define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ |
| 91 | #define CONFIG_ENV_OVERWRITE /* Serial change Ok */ |
| 92 | #define CFG_ENV_ADDR (CFG_RESET_ADDR + CFG_MONITOR_LEN) |
| 93 | |
| 94 | /*------------------------------------------------------------------------ |
| 95 | * CONSOLE |
| 96 | *----------------------------------------------------------------------*/ |
| 97 | #if defined(CONFIG_CONSOLE_JTAG) |
| 98 | #define CFG_NIOS_CONSOLE 0x00920820 /* JTAG UART base addr */ |
| 99 | #else |
| 100 | #define CFG_NIOS_CONSOLE 0x009208a0 /* UART base addr */ |
| 101 | #endif |
| 102 | |
| 103 | #define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ |
| 104 | #define CONFIG_BAUDRATE 115200 /* Initial baudrate */ |
| 105 | #define CFG_BAUDRATE_TABLE {115200} /* It's fixed ;-) */ |
| 106 | |
| 107 | #define CFG_CONSOLE_INFO_QUIET 1 /* Suppress console info*/ |
| 108 | |
| 109 | /*------------------------------------------------------------------------ |
| 110 | * DEBUG |
| 111 | *----------------------------------------------------------------------*/ |
| 112 | #undef CONFIG_ROM_STUBS /* Stubs not in ROM */ |
| 113 | |
| 114 | /*------------------------------------------------------------------------ |
| 115 | * TIMEBASE -- |
| 116 | * |
| 117 | * The high res timer defaults to 1 msec. Since it includes the period |
| 118 | * registers, we can slow it down to 10 msec using TMRCNT. If the default |
| 119 | * period is acceptable, TMRCNT can be left undefined. |
| 120 | *----------------------------------------------------------------------*/ |
| 121 | #define CFG_NIOS_TMRBASE 0x00920860 /* Tick timer base addr */ |
| 122 | #define CFG_NIOS_TMRIRQ 3 /* Timer IRQ num */ |
| 123 | #define CFG_NIOS_TMRMS 10 /* 10 msec per tick */ |
| 124 | #define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) |
| 125 | #define CFG_HZ (CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1)) |
| 126 | |
| 127 | /*------------------------------------------------------------------------ |
| 128 | * STATUS LED -- Provides a simple blinking led. For Nios2 each board |
| 129 | * must implement its own led routines -- leds are, after all, |
| 130 | * board-specific, no? |
| 131 | *----------------------------------------------------------------------*/ |
| 132 | #define CFG_LEDPIO_ADDR 0x00920840 /* LED PIO base addr */ |
| 133 | #define CONFIG_STATUS_LED /* Enable status driver */ |
| 134 | |
| 135 | #define STATUS_LED_BIT 1 /* Bit-0 on PIO */ |
| 136 | #define STATUS_LED_STATE 1 /* Blinking */ |
| 137 | #define STATUS_LED_PERIOD (500/CFG_NIOS_TMRMS) /* Every 500 msec */ |
| 138 | |
| 139 | /*------------------------------------------------------------------------ |
| 140 | * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ... |
| 141 | * and really doesn't need any additional clutter. So I choose the lazy |
| 142 | * way out to avoid changes there -- define the base address to ensure |
| 143 | * cache bypass so there's no need to monkey with inx/outx macros. |
| 144 | *----------------------------------------------------------------------*/ |
| 145 | #define CONFIG_SMC91111_BASE 0x80910300 /* Base addr (bypass) */ |
| 146 | #define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */ |
| 147 | #undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ |
| 148 | #define CONFIG_SMC_USE_32_BIT /* 32-bit interface */ |
| 149 | |
| 150 | #define CONFIG_ETHADDR 08:00:3e:26:0a:5b |
| 151 | #define CONFIG_NETMASK 255.255.255.0 |
| 152 | #define CONFIG_IPADDR 192.168.2.21 |
| 153 | #define CONFIG_SERVERIP 192.168.2.16 |
| 154 | |
| 155 | /*------------------------------------------------------------------------ |
| 156 | * COMMANDS |
| 157 | *----------------------------------------------------------------------*/ |
| 158 | #define CONFIG_COMMANDS (CFG_CMD_BDI | \ |
| 159 | CFG_CMD_DHCP | \ |
| 160 | CFG_CMD_ECHO | \ |
| 161 | CFG_CMD_ENV | \ |
| 162 | CFG_CMD_FLASH | \ |
| 163 | CFG_CMD_IMI | \ |
| 164 | CFG_CMD_IRQ | \ |
| 165 | CFG_CMD_LOADS | \ |
| 166 | CFG_CMD_LOADB | \ |
| 167 | CFG_CMD_MEMORY | \ |
| 168 | CFG_CMD_MISC | \ |
| 169 | CFG_CMD_NET | \ |
| 170 | CFG_CMD_PING | \ |
| 171 | CFG_CMD_RUN | \ |
| 172 | CFG_CMD_SAVES ) |
| 173 | #include <cmd_confdefs.h> |
| 174 | |
| 175 | /*------------------------------------------------------------------------ |
| 176 | * MISC |
| 177 | *----------------------------------------------------------------------*/ |
| 178 | #define CFG_LONGHELP /* Provide extended help*/ |
| 179 | #define CFG_PROMPT "==> " /* Command prompt */ |
| 180 | #define CFG_CBSIZE 256 /* Console I/O buf size */ |
| 181 | #define CFG_MAXARGS 16 /* Max command args */ |
| 182 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot arg buf size */ |
| 183 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */ |
| 184 | #define CFG_LOAD_ADDR CFG_SDRAM_BASE /* Default load address */ |
| 185 | #define CFG_MEMTEST_START CFG_SDRAM_BASE /* Start addr for test */ |
| 186 | #define CFG_MEMTEST_END CFG_INIT_SP - 0x00020000 |
| 187 | |
| 188 | #endif /* __CONFIG_H */ |