blob: 69e299d6a3d357104076ccb423572dda4b718879 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Macpaul Linb3dbf4a52010-12-21 16:59:46 +08002/*
3 * Faraday FTGMAC100 Ethernet
4 *
5 * (C) Copyright 2009 Faraday Technology
6 * Po-Yu Chuang <ratbert@faraday-tech.com>
7 *
8 * (C) Copyright 2010 Andes Technology
9 * Macpaul Lin <macpaul@andestech.com>
Cédric Le Goaterf95de0b2018-10-29 07:06:31 +010010 *
11 * Copyright (C) 2018, IBM Corporation.
Macpaul Linb3dbf4a52010-12-21 16:59:46 +080012 */
13
Simon Glassf7ae49f2020-05-10 11:40:05 -060014#include <common.h>
Cédric Le Goater1c0c61e2018-10-29 07:06:36 +010015#include <clk.h>
Simon Glass1eb69ae2019-11-14 12:57:39 -070016#include <cpu_func.h>
Cédric Le Goaterf95de0b2018-10-29 07:06:31 +010017#include <dm.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060018#include <log.h>
Simon Glass336d4612020-02-03 07:36:16 -070019#include <malloc.h>
Cédric Le Goaterf95de0b2018-10-29 07:06:31 +010020#include <miiphy.h>
Macpaul Linb3dbf4a52010-12-21 16:59:46 +080021#include <net.h>
Cédric Le Goaterd0e0b842018-10-29 07:06:35 +010022#include <wait_bit.h>
Simon Glass90526e92020-05-10 11:39:56 -060023#include <asm/cache.h>
Simon Glass336d4612020-02-03 07:36:16 -070024#include <dm/device_compat.h>
Simon Glasscd93d622020-05-10 11:40:13 -060025#include <linux/bitops.h>
Cédric Le Goaterf95de0b2018-10-29 07:06:31 +010026#include <linux/io.h>
Cédric Le Goater538e75d2018-10-29 07:06:33 +010027#include <linux/iopoll.h>
Macpaul Linb3dbf4a52010-12-21 16:59:46 +080028
29#include "ftgmac100.h"
30
Cédric Le Goatere7668492018-10-29 07:06:34 +010031/* Min frame ethernet frame size without FCS */
32#define ETH_ZLEN 60
Macpaul Linb3dbf4a52010-12-21 16:59:46 +080033
Cédric Le Goatere7668492018-10-29 07:06:34 +010034/* Receive Buffer Size Register - HW default is 0x640 */
35#define FTGMAC100_RBSR_DEFAULT 0x640
Macpaul Linb3dbf4a52010-12-21 16:59:46 +080036
37/* PKTBUFSTX/PKTBUFSRX must both be power of 2 */
38#define PKTBUFSTX 4 /* must be power of 2 */
39
Cédric Le Goaterd0e0b842018-10-29 07:06:35 +010040/* Timeout for transmit */
41#define FTGMAC100_TX_TIMEOUT_MS 1000
42
Cédric Le Goater538e75d2018-10-29 07:06:33 +010043/* Timeout for a mdio read/write operation */
44#define FTGMAC100_MDIO_TIMEOUT_USEC 10000
45
46/*
47 * MDC clock cycle threshold
48 *
49 * 20us * 100 = 2ms > (1 / 2.5Mhz) * 0x34
50 */
51#define MDC_CYCTHR 0x34
52
Cédric Le Goatere6ddacc2018-10-29 07:06:38 +010053/*
54 * ftgmac100 model variants
55 */
56enum ftgmac100_model {
57 FTGMAC100_MODEL_FARADAY,
58 FTGMAC100_MODEL_ASPEED,
59};
60
Cédric Le Goaterf95de0b2018-10-29 07:06:31 +010061/**
62 * struct ftgmac100_data - private data for the FTGMAC100 driver
63 *
64 * @iobase: The base address of the hardware registers
65 * @txdes: The array of transmit descriptors
66 * @rxdes: The array of receive descriptors
67 * @tx_index: Transmit descriptor index in @txdes
68 * @rx_index: Receive descriptor index in @rxdes
69 * @phy_addr: The PHY interface address to use
Cédric Le Goater538e75d2018-10-29 07:06:33 +010070 * @phydev: The PHY device backing the MAC
71 * @bus: The mdio bus
72 * @phy_mode: The mode of the PHY interface (rgmii, rmii, ...)
73 * @max_speed: Maximum speed of Ethernet connection supported by MAC
Cédric Le Goater1c0c61e2018-10-29 07:06:36 +010074 * @clks: The bulk of clocks assigned to the device in the DT
Cédric Le Goatere6ddacc2018-10-29 07:06:38 +010075 * @rxdes0_edorr_mask: The bit number identifying the end of the RX ring buffer
76 * @txdes0_edotr_mask: The bit number identifying the end of the TX ring buffer
Cédric Le Goaterf95de0b2018-10-29 07:06:31 +010077 */
Macpaul Linb3dbf4a52010-12-21 16:59:46 +080078struct ftgmac100_data {
Cédric Le Goaterf95de0b2018-10-29 07:06:31 +010079 struct ftgmac100 *iobase;
80
Cédric Le Goater08b3e902019-11-28 13:37:04 +010081 struct ftgmac100_txdes txdes[PKTBUFSTX] __aligned(ARCH_DMA_MINALIGN);
82 struct ftgmac100_rxdes rxdes[PKTBUFSRX] __aligned(ARCH_DMA_MINALIGN);
Macpaul Linb3dbf4a52010-12-21 16:59:46 +080083 int tx_index;
84 int rx_index;
Cédric Le Goater538e75d2018-10-29 07:06:33 +010085
86 u32 phy_addr;
87 struct phy_device *phydev;
88 struct mii_dev *bus;
89 u32 phy_mode;
90 u32 max_speed;
Cédric Le Goater1c0c61e2018-10-29 07:06:36 +010091
92 struct clk_bulk clks;
Cédric Le Goatere6ddacc2018-10-29 07:06:38 +010093
94 /* End of RX/TX ring buffer bits. Depend on model */
95 u32 rxdes0_edorr_mask;
96 u32 txdes0_edotr_mask;
Macpaul Linb3dbf4a52010-12-21 16:59:46 +080097};
98
99/*
100 * struct mii_bus functions
101 */
Cédric Le Goater538e75d2018-10-29 07:06:33 +0100102static int ftgmac100_mdio_read(struct mii_dev *bus, int phy_addr, int dev_addr,
103 int reg_addr)
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800104{
Cédric Le Goater538e75d2018-10-29 07:06:33 +0100105 struct ftgmac100_data *priv = bus->priv;
Cédric Le Goaterf95de0b2018-10-29 07:06:31 +0100106 struct ftgmac100 *ftgmac100 = priv->iobase;
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800107 int phycr;
108 int data;
Cédric Le Goater538e75d2018-10-29 07:06:33 +0100109 int ret;
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800110
Cédric Le Goater538e75d2018-10-29 07:06:33 +0100111 phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) |
112 FTGMAC100_PHYCR_PHYAD(phy_addr) |
113 FTGMAC100_PHYCR_REGAD(reg_addr) |
114 FTGMAC100_PHYCR_MIIRD;
115 writel(phycr, &ftgmac100->phycr);
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800116
Cédric Le Goater538e75d2018-10-29 07:06:33 +0100117 ret = readl_poll_timeout(&ftgmac100->phycr, phycr,
118 !(phycr & FTGMAC100_PHYCR_MIIRD),
119 FTGMAC100_MDIO_TIMEOUT_USEC);
120 if (ret) {
121 pr_err("%s: mdio read failed (phy:%d reg:%x)\n",
122 priv->phydev->dev->name, phy_addr, reg_addr);
123 return ret;
124 }
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800125
Cédric Le Goater538e75d2018-10-29 07:06:33 +0100126 data = readl(&ftgmac100->phydata);
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800127
Cédric Le Goater538e75d2018-10-29 07:06:33 +0100128 return FTGMAC100_PHYDATA_MIIRDATA(data);
129}
130
131static int ftgmac100_mdio_write(struct mii_dev *bus, int phy_addr, int dev_addr,
132 int reg_addr, u16 value)
133{
134 struct ftgmac100_data *priv = bus->priv;
135 struct ftgmac100 *ftgmac100 = priv->iobase;
136 int phycr;
137 int data;
138 int ret;
139
140 phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) |
141 FTGMAC100_PHYCR_PHYAD(phy_addr) |
142 FTGMAC100_PHYCR_REGAD(reg_addr) |
143 FTGMAC100_PHYCR_MIIWR;
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800144 data = FTGMAC100_PHYDATA_MIIWDATA(value);
145
146 writel(data, &ftgmac100->phydata);
147 writel(phycr, &ftgmac100->phycr);
148
Cédric Le Goater538e75d2018-10-29 07:06:33 +0100149 ret = readl_poll_timeout(&ftgmac100->phycr, phycr,
150 !(phycr & FTGMAC100_PHYCR_MIIWR),
151 FTGMAC100_MDIO_TIMEOUT_USEC);
152 if (ret) {
153 pr_err("%s: mdio write failed (phy:%d reg:%x)\n",
154 priv->phydev->dev->name, phy_addr, reg_addr);
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800155 }
156
Cédric Le Goater538e75d2018-10-29 07:06:33 +0100157 return ret;
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800158}
159
Cédric Le Goater538e75d2018-10-29 07:06:33 +0100160static int ftgmac100_mdio_init(struct udevice *dev)
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800161{
Cédric Le Goater538e75d2018-10-29 07:06:33 +0100162 struct ftgmac100_data *priv = dev_get_priv(dev);
163 struct mii_dev *bus;
164 int ret;
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800165
Cédric Le Goater538e75d2018-10-29 07:06:33 +0100166 bus = mdio_alloc();
167 if (!bus)
168 return -ENOMEM;
169
170 bus->read = ftgmac100_mdio_read;
171 bus->write = ftgmac100_mdio_write;
172 bus->priv = priv;
173
Simon Glass8b85dfc2020-12-16 21:20:07 -0700174 ret = mdio_register_seq(bus, dev_seq(dev));
Cédric Le Goater538e75d2018-10-29 07:06:33 +0100175 if (ret) {
176 free(bus);
177 return ret;
178 }
179
180 priv->bus = bus;
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800181
182 return 0;
183}
184
Cédric Le Goater538e75d2018-10-29 07:06:33 +0100185static int ftgmac100_phy_adjust_link(struct ftgmac100_data *priv)
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800186{
Cédric Le Goaterf95de0b2018-10-29 07:06:31 +0100187 struct ftgmac100 *ftgmac100 = priv->iobase;
Cédric Le Goater538e75d2018-10-29 07:06:33 +0100188 struct phy_device *phydev = priv->phydev;
189 u32 maccr;
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800190
Cédric Le Goater538e75d2018-10-29 07:06:33 +0100191 if (!phydev->link) {
192 dev_err(phydev->dev, "No link\n");
193 return -EREMOTEIO;
194 }
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800195
196 /* read MAC control register and clear related bits */
197 maccr = readl(&ftgmac100->maccr) &
198 ~(FTGMAC100_MACCR_GIGA_MODE |
199 FTGMAC100_MACCR_FAST_MODE |
200 FTGMAC100_MACCR_FULLDUP);
201
Cédric Le Goater538e75d2018-10-29 07:06:33 +0100202 if (phy_interface_is_rgmii(phydev) && phydev->speed == 1000)
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800203 maccr |= FTGMAC100_MACCR_GIGA_MODE;
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800204
Cédric Le Goater538e75d2018-10-29 07:06:33 +0100205 if (phydev->speed == 100)
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800206 maccr |= FTGMAC100_MACCR_FAST_MODE;
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800207
Cédric Le Goater538e75d2018-10-29 07:06:33 +0100208 if (phydev->duplex)
209 maccr |= FTGMAC100_MACCR_FULLDUP;
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800210
211 /* update MII config into maccr */
212 writel(maccr, &ftgmac100->maccr);
213
Cédric Le Goater538e75d2018-10-29 07:06:33 +0100214 return 0;
215}
216
217static int ftgmac100_phy_init(struct udevice *dev)
218{
219 struct ftgmac100_data *priv = dev_get_priv(dev);
220 struct phy_device *phydev;
221 int ret;
222
223 phydev = phy_connect(priv->bus, priv->phy_addr, dev, priv->phy_mode);
224 if (!phydev)
225 return -ENODEV;
226
227 phydev->supported &= PHY_GBIT_FEATURES;
228 if (priv->max_speed) {
229 ret = phy_set_supported(phydev, priv->max_speed);
230 if (ret)
231 return ret;
232 }
233 phydev->advertising = phydev->supported;
234 priv->phydev = phydev;
235 phy_config(phydev);
236
237 return 0;
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800238}
239
240/*
241 * Reset MAC
242 */
Cédric Le Goaterf95de0b2018-10-29 07:06:31 +0100243static void ftgmac100_reset(struct ftgmac100_data *priv)
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800244{
Cédric Le Goaterf95de0b2018-10-29 07:06:31 +0100245 struct ftgmac100 *ftgmac100 = priv->iobase;
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800246
247 debug("%s()\n", __func__);
248
Cédric Le Goater591ffd92018-10-29 07:06:32 +0100249 setbits_le32(&ftgmac100->maccr, FTGMAC100_MACCR_SW_RST);
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800250
251 while (readl(&ftgmac100->maccr) & FTGMAC100_MACCR_SW_RST)
252 ;
253}
254
255/*
256 * Set MAC address
257 */
Cédric Le Goaterf95de0b2018-10-29 07:06:31 +0100258static int ftgmac100_set_mac(struct ftgmac100_data *priv,
259 const unsigned char *mac)
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800260{
Cédric Le Goaterf95de0b2018-10-29 07:06:31 +0100261 struct ftgmac100 *ftgmac100 = priv->iobase;
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800262 unsigned int maddr = mac[0] << 8 | mac[1];
263 unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
264
265 debug("%s(%x %x)\n", __func__, maddr, laddr);
266
267 writel(maddr, &ftgmac100->mac_madr);
268 writel(laddr, &ftgmac100->mac_ladr);
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800269
Cédric Le Goaterf95de0b2018-10-29 07:06:31 +0100270 return 0;
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800271}
272
273/*
274 * disable transmitter, receiver
275 */
Cédric Le Goaterf95de0b2018-10-29 07:06:31 +0100276static void ftgmac100_stop(struct udevice *dev)
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800277{
Cédric Le Goaterf95de0b2018-10-29 07:06:31 +0100278 struct ftgmac100_data *priv = dev_get_priv(dev);
279 struct ftgmac100 *ftgmac100 = priv->iobase;
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800280
281 debug("%s()\n", __func__);
282
283 writel(0, &ftgmac100->maccr);
Cédric Le Goater538e75d2018-10-29 07:06:33 +0100284
285 phy_shutdown(priv->phydev);
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800286}
287
Cédric Le Goaterf95de0b2018-10-29 07:06:31 +0100288static int ftgmac100_start(struct udevice *dev)
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800289{
Simon Glassc69cda22020-12-03 16:55:20 -0700290 struct eth_pdata *plat = dev_get_plat(dev);
Cédric Le Goaterf95de0b2018-10-29 07:06:31 +0100291 struct ftgmac100_data *priv = dev_get_priv(dev);
292 struct ftgmac100 *ftgmac100 = priv->iobase;
Cédric Le Goater538e75d2018-10-29 07:06:33 +0100293 struct phy_device *phydev = priv->phydev;
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800294 unsigned int maccr;
Cédric Le Goatere7668492018-10-29 07:06:34 +0100295 ulong start, end;
Cédric Le Goater538e75d2018-10-29 07:06:33 +0100296 int ret;
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800297 int i;
298
299 debug("%s()\n", __func__);
300
Cédric Le Goaterf95de0b2018-10-29 07:06:31 +0100301 ftgmac100_reset(priv);
302
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800303 /* set the ethernet address */
Cédric Le Goaterf95de0b2018-10-29 07:06:31 +0100304 ftgmac100_set_mac(priv, plat->enetaddr);
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800305
306 /* disable all interrupts */
307 writel(0, &ftgmac100->ier);
308
309 /* initialize descriptors */
310 priv->tx_index = 0;
311 priv->rx_index = 0;
312
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800313 for (i = 0; i < PKTBUFSTX; i++) {
Cédric Le Goatere7668492018-10-29 07:06:34 +0100314 priv->txdes[i].txdes3 = 0;
315 priv->txdes[i].txdes0 = 0;
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800316 }
Cédric Le Goatere6ddacc2018-10-29 07:06:38 +0100317 priv->txdes[PKTBUFSTX - 1].txdes0 = priv->txdes0_edotr_mask;
Cédric Le Goatere7668492018-10-29 07:06:34 +0100318
Cédric Le Goater08b3e902019-11-28 13:37:04 +0100319 start = ((ulong)&priv->txdes[0]) & ~(ARCH_DMA_MINALIGN - 1);
Cédric Le Goatere7668492018-10-29 07:06:34 +0100320 end = start + roundup(sizeof(priv->txdes), ARCH_DMA_MINALIGN);
321 flush_dcache_range(start, end);
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800322
323 for (i = 0; i < PKTBUFSRX; i++) {
Cédric Le Goatere7668492018-10-29 07:06:34 +0100324 priv->rxdes[i].rxdes3 = (unsigned int)net_rx_packets[i];
325 priv->rxdes[i].rxdes0 = 0;
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800326 }
Cédric Le Goatere6ddacc2018-10-29 07:06:38 +0100327 priv->rxdes[PKTBUFSRX - 1].rxdes0 = priv->rxdes0_edorr_mask;
Cédric Le Goatere7668492018-10-29 07:06:34 +0100328
Cédric Le Goater08b3e902019-11-28 13:37:04 +0100329 start = ((ulong)&priv->rxdes[0]) & ~(ARCH_DMA_MINALIGN - 1);
Cédric Le Goatere7668492018-10-29 07:06:34 +0100330 end = start + roundup(sizeof(priv->rxdes), ARCH_DMA_MINALIGN);
331 flush_dcache_range(start, end);
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800332
333 /* transmit ring */
Cédric Le Goatere7668492018-10-29 07:06:34 +0100334 writel((u32)priv->txdes, &ftgmac100->txr_badr);
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800335
336 /* receive ring */
Cédric Le Goatere7668492018-10-29 07:06:34 +0100337 writel((u32)priv->rxdes, &ftgmac100->rxr_badr);
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800338
339 /* poll receive descriptor automatically */
340 writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc);
341
342 /* config receive buffer size register */
Cédric Le Goatere7668492018-10-29 07:06:34 +0100343 writel(FTGMAC100_RBSR_SIZE(FTGMAC100_RBSR_DEFAULT), &ftgmac100->rbsr);
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800344
345 /* enable transmitter, receiver */
346 maccr = FTGMAC100_MACCR_TXMAC_EN |
347 FTGMAC100_MACCR_RXMAC_EN |
348 FTGMAC100_MACCR_TXDMA_EN |
349 FTGMAC100_MACCR_RXDMA_EN |
350 FTGMAC100_MACCR_CRC_APD |
351 FTGMAC100_MACCR_FULLDUP |
352 FTGMAC100_MACCR_RX_RUNT |
353 FTGMAC100_MACCR_RX_BROADPKT;
354
355 writel(maccr, &ftgmac100->maccr);
356
Cédric Le Goater538e75d2018-10-29 07:06:33 +0100357 ret = phy_startup(phydev);
358 if (ret) {
359 dev_err(phydev->dev, "Could not start PHY\n");
360 return ret;
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800361 }
362
Cédric Le Goater538e75d2018-10-29 07:06:33 +0100363 ret = ftgmac100_phy_adjust_link(priv);
364 if (ret) {
365 dev_err(phydev->dev, "Could not adjust link\n");
366 return ret;
367 }
368
369 printf("%s: link up, %d Mbps %s-duplex mac:%pM\n", phydev->dev->name,
370 phydev->speed, phydev->duplex ? "full" : "half", plat->enetaddr);
371
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800372 return 0;
373}
374
Cédric Le Goaterf95de0b2018-10-29 07:06:31 +0100375static int ftgmac100_free_pkt(struct udevice *dev, uchar *packet, int length)
376{
377 struct ftgmac100_data *priv = dev_get_priv(dev);
378 struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index];
Cédric Le Goater08b3e902019-11-28 13:37:04 +0100379 ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1);
Cédric Le Goatere7668492018-10-29 07:06:34 +0100380 ulong des_end = des_start +
381 roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
Cédric Le Goaterf95de0b2018-10-29 07:06:31 +0100382
Cédric Le Goatere7668492018-10-29 07:06:34 +0100383 /* Release buffer to DMA and flush descriptor */
Cédric Le Goaterf95de0b2018-10-29 07:06:31 +0100384 curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
Cédric Le Goatere7668492018-10-29 07:06:34 +0100385 flush_dcache_range(des_start, des_end);
Cédric Le Goaterf95de0b2018-10-29 07:06:31 +0100386
387 /* Move to next descriptor */
388 priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX;
389
390 return 0;
391}
392
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800393/*
394 * Get a data block via Ethernet
395 */
Cédric Le Goaterf95de0b2018-10-29 07:06:31 +0100396static int ftgmac100_recv(struct udevice *dev, int flags, uchar **packetp)
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800397{
Cédric Le Goaterf95de0b2018-10-29 07:06:31 +0100398 struct ftgmac100_data *priv = dev_get_priv(dev);
Cédric Le Goatere7668492018-10-29 07:06:34 +0100399 struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index];
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800400 unsigned short rxlen;
Cédric Le Goater08b3e902019-11-28 13:37:04 +0100401 ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1);
Cédric Le Goatere7668492018-10-29 07:06:34 +0100402 ulong des_end = des_start +
403 roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
404 ulong data_start = curr_des->rxdes3;
405 ulong data_end;
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800406
Cédric Le Goatere7668492018-10-29 07:06:34 +0100407 invalidate_dcache_range(des_start, des_end);
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800408
409 if (!(curr_des->rxdes0 & FTGMAC100_RXDES0_RXPKT_RDY))
Cédric Le Goatere7668492018-10-29 07:06:34 +0100410 return -EAGAIN;
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800411
412 if (curr_des->rxdes0 & (FTGMAC100_RXDES0_RX_ERR |
413 FTGMAC100_RXDES0_CRC_ERR |
414 FTGMAC100_RXDES0_FTL |
415 FTGMAC100_RXDES0_RUNT |
416 FTGMAC100_RXDES0_RX_ODD_NB)) {
Cédric Le Goatere7668492018-10-29 07:06:34 +0100417 return -EAGAIN;
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800418 }
419
420 rxlen = FTGMAC100_RXDES0_VDBC(curr_des->rxdes0);
421
422 debug("%s(): RX buffer %d, %x received\n",
423 __func__, priv->rx_index, rxlen);
424
Cédric Le Goatere7668492018-10-29 07:06:34 +0100425 /* Invalidate received data */
426 data_end = data_start + roundup(rxlen, ARCH_DMA_MINALIGN);
427 invalidate_dcache_range(data_start, data_end);
428 *packetp = (uchar *)data_start;
Kuo-Jung Sua8f9cd12013-05-07 14:33:51 +0800429
Cédric Le Goatere7668492018-10-29 07:06:34 +0100430 return rxlen;
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800431}
432
Cédric Le Goaterd0e0b842018-10-29 07:06:35 +0100433static u32 ftgmac100_read_txdesc(const void *desc)
434{
435 const struct ftgmac100_txdes *txdes = desc;
Cédric Le Goater08b3e902019-11-28 13:37:04 +0100436 ulong des_start = ((ulong)txdes) & ~(ARCH_DMA_MINALIGN - 1);
Cédric Le Goaterd0e0b842018-10-29 07:06:35 +0100437 ulong des_end = des_start + roundup(sizeof(*txdes), ARCH_DMA_MINALIGN);
438
439 invalidate_dcache_range(des_start, des_end);
440
441 return txdes->txdes0;
442}
443
444BUILD_WAIT_FOR_BIT(ftgmac100_txdone, u32, ftgmac100_read_txdesc)
445
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800446/*
447 * Send a data block via Ethernet
448 */
Cédric Le Goaterf95de0b2018-10-29 07:06:31 +0100449static int ftgmac100_send(struct udevice *dev, void *packet, int length)
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800450{
Cédric Le Goaterf95de0b2018-10-29 07:06:31 +0100451 struct ftgmac100_data *priv = dev_get_priv(dev);
452 struct ftgmac100 *ftgmac100 = priv->iobase;
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800453 struct ftgmac100_txdes *curr_des = &priv->txdes[priv->tx_index];
Cédric Le Goater08b3e902019-11-28 13:37:04 +0100454 ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1);
Cédric Le Goatere7668492018-10-29 07:06:34 +0100455 ulong des_end = des_start +
456 roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
457 ulong data_start;
458 ulong data_end;
Cédric Le Goaterd0e0b842018-10-29 07:06:35 +0100459 int rc;
Cédric Le Goatere7668492018-10-29 07:06:34 +0100460
461 invalidate_dcache_range(des_start, des_end);
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800462
463 if (curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN) {
Cédric Le Goatere7668492018-10-29 07:06:34 +0100464 dev_err(dev, "no TX descriptor available\n");
465 return -EPERM;
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800466 }
467
468 debug("%s(%x, %x)\n", __func__, (int)packet, length);
469
470 length = (length < ETH_ZLEN) ? ETH_ZLEN : length;
471
Cédric Le Goatere7668492018-10-29 07:06:34 +0100472 curr_des->txdes3 = (unsigned int)packet;
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800473
Cédric Le Goatere7668492018-10-29 07:06:34 +0100474 /* Flush data to be sent */
475 data_start = curr_des->txdes3;
476 data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
477 flush_dcache_range(data_start, data_end);
478
479 /* Only one segment on TXBUF */
Cédric Le Goatere6ddacc2018-10-29 07:06:38 +0100480 curr_des->txdes0 &= priv->txdes0_edotr_mask;
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800481 curr_des->txdes0 |= FTGMAC100_TXDES0_FTS |
482 FTGMAC100_TXDES0_LTS |
483 FTGMAC100_TXDES0_TXBUF_SIZE(length) |
484 FTGMAC100_TXDES0_TXDMA_OWN ;
485
Cédric Le Goatere7668492018-10-29 07:06:34 +0100486 /* Flush modified buffer descriptor */
487 flush_dcache_range(des_start, des_end);
488
489 /* Start transmit */
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800490 writel(1, &ftgmac100->txpd);
491
Cédric Le Goaterd0e0b842018-10-29 07:06:35 +0100492 rc = wait_for_bit_ftgmac100_txdone(curr_des,
493 FTGMAC100_TXDES0_TXDMA_OWN, false,
494 FTGMAC100_TX_TIMEOUT_MS, true);
495 if (rc)
496 return rc;
497
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800498 debug("%s(): packet sent\n", __func__);
499
Cédric Le Goatere7668492018-10-29 07:06:34 +0100500 /* Move to next descriptor */
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800501 priv->tx_index = (priv->tx_index + 1) % PKTBUFSTX;
502
503 return 0;
504}
505
Cédric Le Goaterf95de0b2018-10-29 07:06:31 +0100506static int ftgmac100_write_hwaddr(struct udevice *dev)
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800507{
Simon Glassc69cda22020-12-03 16:55:20 -0700508 struct eth_pdata *pdata = dev_get_plat(dev);
Cédric Le Goaterf95de0b2018-10-29 07:06:31 +0100509 struct ftgmac100_data *priv = dev_get_priv(dev);
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800510
Cédric Le Goaterf95de0b2018-10-29 07:06:31 +0100511 return ftgmac100_set_mac(priv, pdata->enetaddr);
512}
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800513
Simon Glassd1998a92020-12-03 16:55:21 -0700514static int ftgmac100_of_to_plat(struct udevice *dev)
Cédric Le Goaterf95de0b2018-10-29 07:06:31 +0100515{
Simon Glassc69cda22020-12-03 16:55:20 -0700516 struct eth_pdata *pdata = dev_get_plat(dev);
Cédric Le Goater1c0c61e2018-10-29 07:06:36 +0100517 struct ftgmac100_data *priv = dev_get_priv(dev);
Cédric Le Goater538e75d2018-10-29 07:06:33 +0100518 const char *phy_mode;
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800519
Masahiro Yamada25484932020-07-17 14:36:48 +0900520 pdata->iobase = dev_read_addr(dev);
Cédric Le Goater538e75d2018-10-29 07:06:33 +0100521 pdata->phy_interface = -1;
522 phy_mode = dev_read_string(dev, "phy-mode");
523 if (phy_mode)
524 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
525 if (pdata->phy_interface == -1) {
526 dev_err(dev, "Invalid PHY interface '%s'\n", phy_mode);
527 return -EINVAL;
528 }
529
530 pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
531
Cédric Le Goatere6ddacc2018-10-29 07:06:38 +0100532 if (dev_get_driver_data(dev) == FTGMAC100_MODEL_ASPEED) {
533 priv->rxdes0_edorr_mask = BIT(30);
534 priv->txdes0_edotr_mask = BIT(30);
535 } else {
536 priv->rxdes0_edorr_mask = BIT(15);
537 priv->txdes0_edotr_mask = BIT(15);
538 }
539
Cédric Le Goater1c0c61e2018-10-29 07:06:36 +0100540 return clk_get_bulk(dev, &priv->clks);
Macpaul Linb3dbf4a52010-12-21 16:59:46 +0800541}
Cédric Le Goaterf95de0b2018-10-29 07:06:31 +0100542
543static int ftgmac100_probe(struct udevice *dev)
544{
Simon Glassc69cda22020-12-03 16:55:20 -0700545 struct eth_pdata *pdata = dev_get_plat(dev);
Cédric Le Goaterf95de0b2018-10-29 07:06:31 +0100546 struct ftgmac100_data *priv = dev_get_priv(dev);
Cédric Le Goater538e75d2018-10-29 07:06:33 +0100547 int ret;
Cédric Le Goaterf95de0b2018-10-29 07:06:31 +0100548
549 priv->iobase = (struct ftgmac100 *)pdata->iobase;
Cédric Le Goater538e75d2018-10-29 07:06:33 +0100550 priv->phy_mode = pdata->phy_interface;
551 priv->max_speed = pdata->max_speed;
552 priv->phy_addr = 0;
553
Thirupathaiah Annapureddy66e036b2020-08-17 17:08:26 -0700554#ifdef CONFIG_PHY_ADDR
555 priv->phy_addr = CONFIG_PHY_ADDR;
556#endif
557
Cédric Le Goater1c0c61e2018-10-29 07:06:36 +0100558 ret = clk_enable_bulk(&priv->clks);
559 if (ret)
560 goto out;
561
Cédric Le Goater538e75d2018-10-29 07:06:33 +0100562 ret = ftgmac100_mdio_init(dev);
563 if (ret) {
564 dev_err(dev, "Failed to initialize mdiobus: %d\n", ret);
565 goto out;
566 }
567
568 ret = ftgmac100_phy_init(dev);
569 if (ret) {
570 dev_err(dev, "Failed to initialize PHY: %d\n", ret);
571 goto out;
572 }
573
574out:
Cédric Le Goater1c0c61e2018-10-29 07:06:36 +0100575 if (ret)
576 clk_release_bulk(&priv->clks);
577
Cédric Le Goater538e75d2018-10-29 07:06:33 +0100578 return ret;
Cédric Le Goaterf95de0b2018-10-29 07:06:31 +0100579}
580
581static int ftgmac100_remove(struct udevice *dev)
582{
Cédric Le Goater538e75d2018-10-29 07:06:33 +0100583 struct ftgmac100_data *priv = dev_get_priv(dev);
584
585 free(priv->phydev);
586 mdio_unregister(priv->bus);
587 mdio_free(priv->bus);
Cédric Le Goater1c0c61e2018-10-29 07:06:36 +0100588 clk_release_bulk(&priv->clks);
Cédric Le Goater538e75d2018-10-29 07:06:33 +0100589
Cédric Le Goaterf95de0b2018-10-29 07:06:31 +0100590 return 0;
591}
592
593static const struct eth_ops ftgmac100_ops = {
594 .start = ftgmac100_start,
595 .send = ftgmac100_send,
596 .recv = ftgmac100_recv,
597 .stop = ftgmac100_stop,
598 .free_pkt = ftgmac100_free_pkt,
599 .write_hwaddr = ftgmac100_write_hwaddr,
600};
601
602static const struct udevice_id ftgmac100_ids[] = {
Cédric Le Goatere6ddacc2018-10-29 07:06:38 +0100603 { .compatible = "faraday,ftgmac100", .data = FTGMAC100_MODEL_FARADAY },
604 { .compatible = "aspeed,ast2500-mac", .data = FTGMAC100_MODEL_ASPEED },
Cédric Le Goaterf95de0b2018-10-29 07:06:31 +0100605 { }
606};
607
608U_BOOT_DRIVER(ftgmac100) = {
609 .name = "ftgmac100",
610 .id = UCLASS_ETH,
611 .of_match = ftgmac100_ids,
Simon Glassd1998a92020-12-03 16:55:21 -0700612 .of_to_plat = ftgmac100_of_to_plat,
Cédric Le Goaterf95de0b2018-10-29 07:06:31 +0100613 .probe = ftgmac100_probe,
614 .remove = ftgmac100_remove,
615 .ops = &ftgmac100_ops,
Simon Glass41575d82020-12-03 16:55:17 -0700616 .priv_auto = sizeof(struct ftgmac100_data),
Simon Glasscaa4daa2020-12-03 16:55:18 -0700617 .plat_auto = sizeof(struct eth_pdata),
Cédric Le Goaterf95de0b2018-10-29 07:06:31 +0100618 .flags = DM_FLAG_ALLOC_PRIV_DMA,
619};