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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -06002/*
3 * Configuation settings for the Freescale MCF5373 FireEngine board.
4 *
Alison Wang2ee03c62012-03-25 19:18:14 +00005 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
TsiChungLiewaa5f1f92008-01-14 17:23:08 -06006 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
TsiChungLiewaa5f1f92008-01-14 17:23:08 -06007 */
8
9/*
10 * board/config.h - configuration options, board specific
11 */
12
13#ifndef _M5373EVB_H
14#define _M5373EVB_H
15
Simon Glass1af3c7f2020-05-10 11:40:09 -060016#include <linux/stringify.h>
17
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060018/*
19 * High Level Configuration Options
20 * (easy to change)
21 */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060022
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060023#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020024#define CONFIG_SYS_UART_PORT (0)
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060025
26#undef CONFIG_WATCHDOG
27#define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */
28
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020029#define CONFIG_SYS_UNIFY_CACHE
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060030
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060031#ifdef CONFIG_MCFFEC
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -050032# define CONFIG_MII_INIT 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020033# define CONFIG_SYS_DISCOVER_PHY
34# define CONFIG_SYS_RX_ETH_BUFFER 8
35# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020036/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
37# ifndef CONFIG_SYS_DISCOVER_PHY
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060038# define FECDUPLEX FULL
39# define FECSPEED _100BASET
40# else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
42# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060043# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020044# endif /* CONFIG_SYS_DISCOVER_PHY */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060045#endif
46
47#define CONFIG_MCFRTC
48#undef RTC_DEBUG
49
50/* Timer */
51#define CONFIG_MCFTMR
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060052
53/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +020054#define CONFIG_SYS_I2C
55#define CONFIG_SYS_I2C_FSL
56#define CONFIG_SYS_FSL_I2C_SPEED 80000
57#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
58#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060060
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060061#define CONFIG_UDP_CHECKSUM
62
63#ifdef CONFIG_MCFFEC
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060064# define CONFIG_IPADDR 192.162.1.2
65# define CONFIG_NETMASK 255.255.255.0
66# define CONFIG_SERVERIP 192.162.1.1
67# define CONFIG_GATEWAYIP 192.162.1.1
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060068#endif /* FEC_ENET */
69
Mario Six5bc05432018-03-28 14:38:20 +020070#define CONFIG_HOSTNAME "M5373EVB"
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060071#define CONFIG_EXTRA_ENV_SETTINGS \
72 "netdev=eth0\0" \
Marek Vasut5368c552012-09-23 17:41:24 +020073 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060074 "u-boot=u-boot.bin\0" \
75 "load=tftp ${loadaddr) ${u-boot}\0" \
76 "upd=run load; run prog\0" \
Jason Jin09933fb2011-08-19 10:10:40 +080077 "prog=prot off 0 3ffff;" \
78 "era 0 3ffff;" \
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060079 "cp.b ${loadaddr} 0 ${filesize};" \
80 "save\0" \
81 ""
82
83#define CONFIG_PRAM 512 /* 512 KB */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060084
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#define CONFIG_SYS_LOAD_ADDR 0x40010000
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060086
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087#define CONFIG_SYS_CLK 80000000
88#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060089
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CONFIG_SYS_MBAR 0xFC000000
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060091
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)
TsiChungLiewaa5f1f92008-01-14 17:23:08 -060093
94/*
95 * Low Level Configuration Settings
96 * (address mappings, register initial values, etc.)
97 * You should know what you are doing if you make changes here.
98 */
99/*-----------------------------------------------------------------------
100 * Definitions for initial stack pointer and data area (in DPRAM)
101 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200103#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_INIT_RAM_CTRL 0x221
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200105#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600107
108/*-----------------------------------------------------------------------
109 * Start addresses for the final memory configuration
110 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600112 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_SDRAM_BASE 0x40000000
114#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
115#define CONFIG_SYS_SDRAM_CFG1 0x53722730
116#define CONFIG_SYS_SDRAM_CFG2 0x56670000
117#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
118#define CONFIG_SYS_SDRAM_EMOD 0x40010000
119#define CONFIG_SYS_SDRAM_MODE 0x018D0000
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600120
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
122#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600123
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
125#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600126
127/*
128 * For booting Linux, the board info and command line data
129 * have to be in the first 8 MB of memory, since this is
130 * the maximum mapped by the Linux kernel during initialization ??
131 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
TsiChung Liewd6e4baf2009-01-27 12:57:47 +0000133#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600134
135/*-----------------------------------------------------------------------
136 * FLASH organization
137 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#ifdef CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
140# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
141# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
142# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600143#endif
144
Alison Wang2ee03c62012-03-25 19:18:14 +0000145#ifdef CONFIG_NANDFLASH_SIZE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146# define CONFIG_SYS_MAX_NAND_DEVICE 1
147# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
148# define CONFIG_SYS_NAND_SIZE 1
149# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600150# define NAND_ALLOW_ERASE_ALL 1
151# define CONFIG_JFFS2_NAND 1
152# define CONFIG_JFFS2_DEV "nand0"
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153# define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1)
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600154# define CONFIG_JFFS2_PART_OFFSET 0x00000000
155#endif
156
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600158
159/* Configuration for environment
160 * Environment is embedded in u-boot in the second sector of the flash
161 */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600162
angelo@sysam.it5296cb12015-03-29 22:54:16 +0200163#define LDS_BOARD_TEXT \
Simon Glass0649cd02017-08-03 12:21:49 -0600164 . = DEFINED(env_offset) ? env_offset : .; \
165 env/embedded.o(.text*);
angelo@sysam.it5296cb12015-03-29 22:54:16 +0200166
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600167/*-----------------------------------------------------------------------
168 * Cache Configuration
169 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_CACHELINE_SIZE 16
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600171
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600172#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200173 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600174#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200175 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600176#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
177#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
178 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
179 CF_ACR_EN | CF_ACR_SM_ALL)
180#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
181 CF_CACR_DCM_P)
182
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600183/*-----------------------------------------------------------------------
184 * Chipselect bank definitions
185 */
186/*
187 * CS0 - NOR Flash 1, 2, 4, or 8MB
188 * CS1 - CompactFlash and registers
189 * CS2 - NAND Flash 16, 32, or 64MB
190 * CS3 - Available
191 * CS4 - Available
192 * CS5 - Available
193 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_CS0_BASE 0
195#define CONFIG_SYS_CS0_MASK 0x007f0001
196#define CONFIG_SYS_CS0_CTRL 0x00001fa0
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600197
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_CS1_BASE 0x10000000
199#define CONFIG_SYS_CS1_MASK 0x001f0001
200#define CONFIG_SYS_CS1_CTRL 0x002A3780
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600201
Alison Wang2ee03c62012-03-25 19:18:14 +0000202#ifdef CONFIG_NANDFLASH_SIZE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_CS2_BASE 0x20000000
Alison Wang2ee03c62012-03-25 19:18:14 +0000204#define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_CS2_CTRL 0x00001f60
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600206#endif
207
208#endif /* _M5373EVB_H */