| stroese | 46578cc | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 1 | /*------------------------------------------------------------------------------+ */ |
| 2 | /* */ |
| 3 | /* This source code has been made available to you by IBM on an AS-IS */ |
| 4 | /* basis. Anyone receiving this source is licensed under IBM */ |
| 5 | /* copyrights to use it in any way he or she deems fit, including */ |
| 6 | /* copying it, modifying it, compiling it, and redistributing it either */ |
| 7 | /* with or without modifications. No license under IBM patents or */ |
| 8 | /* patent applications is to be implied by the copyright license. */ |
| 9 | /* */ |
| 10 | /* Any user of this software should understand that IBM cannot provide */ |
| 11 | /* technical support for this software and will not be responsible for */ |
| 12 | /* any consequences resulting from the use of this software. */ |
| 13 | /* */ |
| 14 | /* Any person who transfers this source code or any derivative work */ |
| 15 | /* must include the IBM copyright notice, this paragraph, and the */ |
| 16 | /* preceding two paragraphs in the transferred software. */ |
| 17 | /* */ |
| 18 | /* COPYRIGHT I B M CORPORATION 1995 */ |
| 19 | /* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */ |
| 20 | /*------------------------------------------------------------------------------- */ |
| 21 | |
| 22 | /*----------------------------------------------------------------------------- */ |
| 23 | /* Function: ext_bus_cntlr_init */ |
| 24 | /* Description: Initializes the External Bus Controller for the external */ |
| 25 | /* peripherals. IMPORTANT: For pass1 this code must run from */ |
| 26 | /* cache since you can not reliably change a peripheral banks */ |
| 27 | /* timing register (pbxap) while running code from that bank. */ |
| 28 | /* For ex., since we are running from ROM on bank 0, we can NOT */ |
| 29 | /* execute the code that modifies bank 0 timings from ROM, so */ |
| 30 | /* we run it from cache. */ |
| 31 | /* Bank 0 - Flash and SRAM */ |
| 32 | /* Bank 1 - NVRAM/RTC */ |
| 33 | /* Bank 2 - Keyboard/Mouse controller */ |
| 34 | /* Bank 3 - IR controller */ |
| 35 | /* Bank 4 - not used */ |
| 36 | /* Bank 5 - not used */ |
| 37 | /* Bank 6 - not used */ |
| 38 | /* Bank 7 - FPGA registers */ |
| 39 | /*----------------------------------------------------------------------------- */ |
| 40 | #include <ppc4xx.h> |
| 41 | |
| 42 | #include <ppc_asm.tmpl> |
| 43 | #include <ppc_defs.h> |
| 44 | |
| 45 | #include <asm/cache.h> |
| 46 | #include <asm/mmu.h> |
| 47 | |
| 48 | |
| 49 | /*----------------------------------------------------------------------------- */ |
| 50 | /* Function: sdram_init */ |
| 51 | /* Description: Dummy implementation here - done in C later */ |
| 52 | /*----------------------------------------------------------------------------- */ |
| wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame^] | 53 | .globl sdram_init |
| stroese | 46578cc | 2003-05-23 11:28:55 +0000 | [diff] [blame] | 54 | sdram_init: |
| wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame^] | 55 | blr |