blob: 08b1bfde72a15476d25320d384e790b1e4f5d29c [file] [log] [blame]
wdenk3e386912003-04-05 00:53:31 +00001/*
2 * Copyright (C) 2003 ETC s.r.o.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17 * MA 02111-1307 USA
18 *
19 * Written by Peter Figuli <peposh@etc.sk>, 2003.
20 *
21 */
22
23#include <common.h>
24#include <asm/arch/pxa-regs.h>
25
26int board_init( void ){
27 DECLARE_GLOBAL_DATA_PTR;
28
wdenk8bde7f72003-06-27 21:31:46 +000029 gd->bd->bi_arch_number = 288;
wdenk3e386912003-04-05 00:53:31 +000030 gd->bd->bi_boot_params = 0xa0000000;
31/*
32 * Setup GPIO stuff to get serial working
33 */
34#if defined( CONFIG_FFUART )
35 GPDR1 = 0x80;
36 GAFR1_L = 0x8010;
37#elif defined( CONFIG_BTUART )
38 GPDR1 = 0x800;
39 GAFR1_L = 0x900000;
40#endif
41 PSSR = 0x20;
42
43/*
44 * Following code is just bug workaround, remove it if not neccessary
45 */
46
47 /* cpu/xscale/cpu.c do not set armboot_real_end that is used for
48 malloc pool.*/
49 if( _armboot_real_end == 0xbadc0de ){
50 _armboot_real_end = _armboot_end;
51 }
52 return 0;
53}
54
55int dram_init( void ){
56 DECLARE_GLOBAL_DATA_PTR;
57
58#if ( CONFIG_NR_DRAM_BANKS > 0 )
59 gd->bd->bi_dram[0].start = WEP_SDRAM_1;
60 gd->bd->bi_dram[0].size = WEP_SDRAM_1_SIZE;
61#endif
wdenk8bde7f72003-06-27 21:31:46 +000062#if ( CONFIG_NR_DRAM_BANKS > 1 )
wdenk3e386912003-04-05 00:53:31 +000063 gd->bd->bi_dram[1].start = WEP_SDRAM_2;
64 gd->bd->bi_dram[1].size = WEP_SDRAM_2_SIZE;
65#endif
wdenk8bde7f72003-06-27 21:31:46 +000066#if ( CONFIG_NR_DRAM_BANKS > 2 )
wdenk3e386912003-04-05 00:53:31 +000067 gd->bd->bi_dram[2].start = WEP_SDRAM_3;
68 gd->bd->bi_dram[2].size = WEP_SDRAM_3_SIZE;
69#endif
70#if ( CONFIG_NR_DRAM_BANKS > 3 )
71 gd->bd->bi_dram[3].start = WEP_SDRAM_4;
72 gd->bd->bi_dram[3].size = WEP_SDRAM_4_SIZE;
73#endif
wdenk8bde7f72003-06-27 21:31:46 +000074
wdenk3e386912003-04-05 00:53:31 +000075 return 0;
76}