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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Alison Wang427eba72013-05-27 22:55:45 +00002/*
Vabhav Sharma1edc5682019-01-31 12:08:10 +00003 * Copyright 2019 NXP
Alison Wang427eba72013-05-27 22:55:45 +00004 * Copyright 2013 Freescale Semiconductor, Inc.
Alison Wang427eba72013-05-27 22:55:45 +00005 */
6
7#include <common.h>
Peng Fan8f5b6292018-10-19 00:26:23 +02008#include <clk.h>
Bin Mengfdbae092016-01-13 19:39:04 -08009#include <dm.h>
Peng Fanc40d6122017-02-22 16:21:51 +080010#include <fsl_lpuart.h>
Alison Wang427eba72013-05-27 22:55:45 +000011#include <watchdog.h>
12#include <asm/io.h>
13#include <serial.h>
14#include <linux/compiler.h>
15#include <asm/arch/imx-regs.h>
16#include <asm/arch/clock.h>
17
Bin Meng47f1bfc2016-01-13 19:39:01 -080018#define US1_TDRE (1 << 7)
19#define US1_RDRF (1 << 5)
20#define US1_OR (1 << 3)
21#define UC2_TE (1 << 3)
22#define UC2_RE (1 << 2)
23#define CFIFO_TXFLUSH (1 << 7)
24#define CFIFO_RXFLUSH (1 << 6)
25#define SFIFO_RXOF (1 << 2)
26#define SFIFO_RXUF (1 << 0)
Alison Wang427eba72013-05-27 22:55:45 +000027
Jingchang Lu6209e142014-09-05 13:52:47 +080028#define STAT_LBKDIF (1 << 31)
29#define STAT_RXEDGIF (1 << 30)
30#define STAT_TDRE (1 << 23)
31#define STAT_RDRF (1 << 21)
32#define STAT_IDLE (1 << 20)
33#define STAT_OR (1 << 19)
34#define STAT_NF (1 << 18)
35#define STAT_FE (1 << 17)
36#define STAT_PF (1 << 16)
37#define STAT_MA1F (1 << 15)
38#define STAT_MA2F (1 << 14)
39#define STAT_FLAGS (STAT_LBKDIF | STAT_RXEDGIF | STAT_IDLE | STAT_OR | \
Bin Meng47f1bfc2016-01-13 19:39:01 -080040 STAT_NF | STAT_FE | STAT_PF | STAT_MA1F | STAT_MA2F)
Jingchang Lu6209e142014-09-05 13:52:47 +080041
42#define CTRL_TE (1 << 19)
43#define CTRL_RE (1 << 18)
44
Ye Licdc16f62018-10-18 14:28:32 +020045#define FIFO_RXFLUSH BIT(14)
46#define FIFO_TXFLUSH BIT(15)
47#define FIFO_TXSIZE_MASK 0x70
48#define FIFO_TXSIZE_OFF 4
49#define FIFO_RXSIZE_MASK 0x7
50#define FIFO_RXSIZE_OFF 0
Jingchang Lu6209e142014-09-05 13:52:47 +080051#define FIFO_TXFE 0x80
Peng Fan126f8842018-10-18 14:28:31 +020052#ifdef CONFIG_ARCH_IMX8
53#define FIFO_RXFE 0x08
54#else
Jingchang Lu6209e142014-09-05 13:52:47 +080055#define FIFO_RXFE 0x40
Peng Fan126f8842018-10-18 14:28:31 +020056#endif
Jingchang Lu6209e142014-09-05 13:52:47 +080057
Ye Licdc16f62018-10-18 14:28:32 +020058#define WATER_TXWATER_OFF 0
Jingchang Lu6209e142014-09-05 13:52:47 +080059#define WATER_RXWATER_OFF 16
60
Alison Wang427eba72013-05-27 22:55:45 +000061DECLARE_GLOBAL_DATA_PTR;
62
Peng Fanc40d6122017-02-22 16:21:51 +080063#define LPUART_FLAG_REGMAP_32BIT_REG BIT(0)
64#define LPUART_FLAG_REGMAP_ENDIAN_BIG BIT(1)
65
Peng Fan7edf5c42017-02-22 16:21:52 +080066enum lpuart_devtype {
67 DEV_VF610 = 1,
68 DEV_LS1021A,
Peng Fan126f8842018-10-18 14:28:31 +020069 DEV_MX7ULP,
70 DEV_IMX8
Peng Fan7edf5c42017-02-22 16:21:52 +080071};
72
Bin Mengfdbae092016-01-13 19:39:04 -080073struct lpuart_serial_platdata {
Peng Fanc40d6122017-02-22 16:21:51 +080074 void *reg;
Peng Fan7edf5c42017-02-22 16:21:52 +080075 enum lpuart_devtype devtype;
Peng Fanc40d6122017-02-22 16:21:51 +080076 ulong flags;
Bin Mengfdbae092016-01-13 19:39:04 -080077};
78
Peng Fanc40d6122017-02-22 16:21:51 +080079static void lpuart_read32(u32 flags, u32 *addr, u32 *val)
Alison Wang427eba72013-05-27 22:55:45 +000080{
Peng Fanc40d6122017-02-22 16:21:51 +080081 if (flags & LPUART_FLAG_REGMAP_32BIT_REG) {
82 if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG)
83 *(u32 *)val = in_be32(addr);
84 else
85 *(u32 *)val = in_le32(addr);
86 }
87}
88
89static void lpuart_write32(u32 flags, u32 *addr, u32 val)
90{
91 if (flags & LPUART_FLAG_REGMAP_32BIT_REG) {
92 if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG)
93 out_be32(addr, val);
94 else
95 out_le32(addr, val);
96 }
97}
98
99
100#ifndef CONFIG_SYS_CLK_FREQ
101#define CONFIG_SYS_CLK_FREQ 0
102#endif
103
104u32 __weak get_lpuart_clk(void)
105{
106 return CONFIG_SYS_CLK_FREQ;
107}
108
Peng Fan8f5b6292018-10-19 00:26:23 +0200109#if IS_ENABLED(CONFIG_CLK)
110static int get_lpuart_clk_rate(struct udevice *dev, u32 *clk)
111{
112 struct clk per_clk;
113 ulong rate;
114 int ret;
115
116 ret = clk_get_by_name(dev, "per", &per_clk);
117 if (ret) {
118 dev_err(dev, "Failed to get per clk: %d\n", ret);
119 return ret;
120 }
121
122 rate = clk_get_rate(&per_clk);
123 if ((long)rate <= 0) {
124 dev_err(dev, "Failed to get per clk rate: %ld\n", (long)rate);
125 return ret;
126 }
127 *clk = rate;
128 return 0;
129}
130#else
131static inline int get_lpuart_clk_rate(struct udevice *dev, u32 *clk)
132{ return -ENOSYS; }
133#endif
134
Peng Fanc40d6122017-02-22 16:21:51 +0800135static bool is_lpuart32(struct udevice *dev)
136{
137 struct lpuart_serial_platdata *plat = dev->platdata;
138
139 return plat->flags & LPUART_FLAG_REGMAP_32BIT_REG;
140}
141
Peng Fan8f5b6292018-10-19 00:26:23 +0200142static void _lpuart_serial_setbrg(struct udevice *dev,
Peng Fanc40d6122017-02-22 16:21:51 +0800143 int baudrate)
144{
Peng Fan8f5b6292018-10-19 00:26:23 +0200145 struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
Peng Fanc40d6122017-02-22 16:21:51 +0800146 struct lpuart_fsl *base = plat->reg;
Peng Fan8f5b6292018-10-19 00:26:23 +0200147 u32 clk;
Alison Wang427eba72013-05-27 22:55:45 +0000148 u16 sbr;
Peng Fan8f5b6292018-10-19 00:26:23 +0200149 int ret;
150
151 if (IS_ENABLED(CONFIG_CLK)) {
152 ret = get_lpuart_clk_rate(dev, &clk);
153 if (ret)
154 return;
155 } else {
156 clk = get_lpuart_clk();
157 }
Alison Wang427eba72013-05-27 22:55:45 +0000158
Bin Meng6ca13b12016-01-13 19:39:03 -0800159 sbr = (u16)(clk / (16 * baudrate));
Alison Wang427eba72013-05-27 22:55:45 +0000160
Bin Meng47f1bfc2016-01-13 19:39:01 -0800161 /* place adjustment later - n/32 BRFA */
Alison Wang427eba72013-05-27 22:55:45 +0000162 __raw_writeb(sbr >> 8, &base->ubdh);
163 __raw_writeb(sbr & 0xff, &base->ubdl);
164}
165
Peng Fanc40d6122017-02-22 16:21:51 +0800166static int _lpuart_serial_getc(struct lpuart_serial_platdata *plat)
Alison Wang427eba72013-05-27 22:55:45 +0000167{
Peng Fanc40d6122017-02-22 16:21:51 +0800168 struct lpuart_fsl *base = plat->reg;
Stefan Agnera3db78d2014-08-19 17:54:27 +0200169 while (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR)))
Alison Wang427eba72013-05-27 22:55:45 +0000170 WATCHDOG_RESET();
171
Stefan Agnera3db78d2014-08-19 17:54:27 +0200172 barrier();
Alison Wang427eba72013-05-27 22:55:45 +0000173
174 return __raw_readb(&base->ud);
175}
176
Peng Fanc40d6122017-02-22 16:21:51 +0800177static void _lpuart_serial_putc(struct lpuart_serial_platdata *plat,
178 const char c)
Alison Wang427eba72013-05-27 22:55:45 +0000179{
Peng Fanc40d6122017-02-22 16:21:51 +0800180 struct lpuart_fsl *base = plat->reg;
181
Alison Wang427eba72013-05-27 22:55:45 +0000182 while (!(__raw_readb(&base->us1) & US1_TDRE))
183 WATCHDOG_RESET();
184
185 __raw_writeb(c, &base->ud);
186}
187
Bin Meng47f1bfc2016-01-13 19:39:01 -0800188/* Test whether a character is in the RX buffer */
Peng Fanc40d6122017-02-22 16:21:51 +0800189static int _lpuart_serial_tstc(struct lpuart_serial_platdata *plat)
Alison Wang427eba72013-05-27 22:55:45 +0000190{
Peng Fanc40d6122017-02-22 16:21:51 +0800191 struct lpuart_fsl *base = plat->reg;
192
Alison Wang427eba72013-05-27 22:55:45 +0000193 if (__raw_readb(&base->urcfifo) == 0)
194 return 0;
195
196 return 1;
197}
198
199/*
200 * Initialise the serial port with the given baudrate. The settings
201 * are always 8 data bits, no parity, 1 stop bit, no start bits.
202 */
Peng Fan8f5b6292018-10-19 00:26:23 +0200203static int _lpuart_serial_init(struct udevice *dev)
Alison Wang427eba72013-05-27 22:55:45 +0000204{
Peng Fan8f5b6292018-10-19 00:26:23 +0200205 struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
Peng Fanc40d6122017-02-22 16:21:51 +0800206 struct lpuart_fsl *base = (struct lpuart_fsl *)plat->reg;
Alison Wang427eba72013-05-27 22:55:45 +0000207 u8 ctrl;
208
209 ctrl = __raw_readb(&base->uc2);
210 ctrl &= ~UC2_RE;
211 ctrl &= ~UC2_TE;
212 __raw_writeb(ctrl, &base->uc2);
213
214 __raw_writeb(0, &base->umodem);
215 __raw_writeb(0, &base->uc1);
216
Stefan Agner89e69fd2014-08-19 17:54:28 +0200217 /* Disable FIFO and flush buffer */
218 __raw_writeb(0x0, &base->upfifo);
219 __raw_writeb(0x0, &base->utwfifo);
220 __raw_writeb(0x1, &base->urwfifo);
221 __raw_writeb(CFIFO_TXFLUSH | CFIFO_RXFLUSH, &base->ucfifo);
222
Alison Wang427eba72013-05-27 22:55:45 +0000223 /* provide data bits, parity, stop bit, etc */
Peng Fan8f5b6292018-10-19 00:26:23 +0200224 _lpuart_serial_setbrg(dev, gd->baudrate);
Alison Wang427eba72013-05-27 22:55:45 +0000225
226 __raw_writeb(UC2_RE | UC2_TE, &base->uc2);
227
228 return 0;
229}
230
Peng Fan8f5b6292018-10-19 00:26:23 +0200231static void _lpuart32_serial_setbrg_7ulp(struct udevice *dev,
Peng Fan7edf5c42017-02-22 16:21:52 +0800232 int baudrate)
233{
Peng Fan8f5b6292018-10-19 00:26:23 +0200234 struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
Peng Fan7edf5c42017-02-22 16:21:52 +0800235 struct lpuart_fsl_reg32 *base = plat->reg;
236 u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
Peng Fan8f5b6292018-10-19 00:26:23 +0200237 u32 clk;
238 int ret;
239
240 if (IS_ENABLED(CONFIG_CLK)) {
241 ret = get_lpuart_clk_rate(dev, &clk);
242 if (ret)
243 return;
244 } else {
245 clk = get_lpuart_clk();
246 }
Peng Fan7edf5c42017-02-22 16:21:52 +0800247
248 baud_diff = baudrate;
249 osr = 0;
250 sbr = 0;
251
252 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
253 tmp_sbr = (clk / (baudrate * tmp_osr));
254
255 if (tmp_sbr == 0)
256 tmp_sbr = 1;
257
258 /*calculate difference in actual buad w/ current values */
259 tmp_diff = (clk / (tmp_osr * tmp_sbr));
260 tmp_diff = tmp_diff - baudrate;
261
262 /* select best values between sbr and sbr+1 */
263 if (tmp_diff > (baudrate - (clk / (tmp_osr * (tmp_sbr + 1))))) {
264 tmp_diff = baudrate - (clk / (tmp_osr * (tmp_sbr + 1)));
265 tmp_sbr++;
266 }
267
268 if (tmp_diff <= baud_diff) {
269 baud_diff = tmp_diff;
270 osr = tmp_osr;
271 sbr = tmp_sbr;
272 }
273 }
274
275 /*
276 * TODO: handle buadrate outside acceptable rate
277 * if (baudDiff > ((config->baudRate_Bps / 100) * 3))
278 * {
279 * Unacceptable baud rate difference of more than 3%
280 * return kStatus_LPUART_BaudrateNotSupport;
281 * }
282 */
283 tmp = in_le32(&base->baud);
284
285 if ((osr > 3) && (osr < 8))
286 tmp |= LPUART_BAUD_BOTHEDGE_MASK;
287
288 tmp &= ~LPUART_BAUD_OSR_MASK;
289 tmp |= LPUART_BAUD_OSR(osr-1);
290
291 tmp &= ~LPUART_BAUD_SBR_MASK;
292 tmp |= LPUART_BAUD_SBR(sbr);
293
294 /* explicitly disable 10 bit mode & set 1 stop bit */
295 tmp &= ~(LPUART_BAUD_M10_MASK | LPUART_BAUD_SBNS_MASK);
296
297 out_le32(&base->baud, tmp);
298}
299
Peng Fan8f5b6292018-10-19 00:26:23 +0200300static void _lpuart32_serial_setbrg(struct udevice *dev,
Peng Fanc40d6122017-02-22 16:21:51 +0800301 int baudrate)
Bin Mengfdbae092016-01-13 19:39:04 -0800302{
Peng Fan8f5b6292018-10-19 00:26:23 +0200303 struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
Peng Fanc40d6122017-02-22 16:21:51 +0800304 struct lpuart_fsl_reg32 *base = plat->reg;
Peng Fan8f5b6292018-10-19 00:26:23 +0200305 u32 clk;
Jingchang Lu6209e142014-09-05 13:52:47 +0800306 u32 sbr;
Peng Fan8f5b6292018-10-19 00:26:23 +0200307 int ret;
308
309 if (IS_ENABLED(CONFIG_CLK)) {
310 ret = get_lpuart_clk_rate(dev, &clk);
311 if (ret)
312 return;
313 } else {
314 clk = get_lpuart_clk();
315 }
Jingchang Lu6209e142014-09-05 13:52:47 +0800316
Bin Meng6ca13b12016-01-13 19:39:03 -0800317 sbr = (clk / (16 * baudrate));
Jingchang Lu6209e142014-09-05 13:52:47 +0800318
Bin Meng47f1bfc2016-01-13 19:39:01 -0800319 /* place adjustment later - n/32 BRFA */
Peng Fanc40d6122017-02-22 16:21:51 +0800320 lpuart_write32(plat->flags, &base->baud, sbr);
Jingchang Lu6209e142014-09-05 13:52:47 +0800321}
322
Peng Fanc40d6122017-02-22 16:21:51 +0800323static int _lpuart32_serial_getc(struct lpuart_serial_platdata *plat)
Jingchang Lu6209e142014-09-05 13:52:47 +0800324{
Peng Fanc40d6122017-02-22 16:21:51 +0800325 struct lpuart_fsl_reg32 *base = plat->reg;
Peng Fan7edf5c42017-02-22 16:21:52 +0800326 u32 stat, val;
Jingchang Lu6209e142014-09-05 13:52:47 +0800327
Peng Fanc40d6122017-02-22 16:21:51 +0800328 lpuart_read32(plat->flags, &base->stat, &stat);
329 while ((stat & STAT_RDRF) == 0) {
330 lpuart_write32(plat->flags, &base->stat, STAT_FLAGS);
331 WATCHDOG_RESET();
332 lpuart_read32(plat->flags, &base->stat, &stat);
333 }
334
Peng Fan7edf5c42017-02-22 16:21:52 +0800335 lpuart_read32(plat->flags, &base->data, &val);
Peng Fanc40d6122017-02-22 16:21:51 +0800336
Sriram Dasha2bbfc52018-01-10 11:57:14 +0530337 lpuart_read32(plat->flags, &base->stat, &stat);
338 if (stat & STAT_OR)
339 lpuart_write32(plat->flags, &base->stat, STAT_OR);
Peng Fan7edf5c42017-02-22 16:21:52 +0800340
341 return val & 0x3ff;
Peng Fanc40d6122017-02-22 16:21:51 +0800342}
343
344static void _lpuart32_serial_putc(struct lpuart_serial_platdata *plat,
345 const char c)
346{
347 struct lpuart_fsl_reg32 *base = plat->reg;
348 u32 stat;
349
Sriram Dasha2bbfc52018-01-10 11:57:14 +0530350 if (c == '\n')
351 serial_putc('\r');
Peng Fan7edf5c42017-02-22 16:21:52 +0800352
Peng Fanc40d6122017-02-22 16:21:51 +0800353 while (true) {
354 lpuart_read32(plat->flags, &base->stat, &stat);
355
356 if ((stat & STAT_TDRE))
357 break;
358
Jingchang Lu6209e142014-09-05 13:52:47 +0800359 WATCHDOG_RESET();
360 }
361
Peng Fanc40d6122017-02-22 16:21:51 +0800362 lpuart_write32(plat->flags, &base->data, c);
Jingchang Lu6209e142014-09-05 13:52:47 +0800363}
364
Bin Meng47f1bfc2016-01-13 19:39:01 -0800365/* Test whether a character is in the RX buffer */
Peng Fanc40d6122017-02-22 16:21:51 +0800366static int _lpuart32_serial_tstc(struct lpuart_serial_platdata *plat)
Jingchang Lu6209e142014-09-05 13:52:47 +0800367{
Peng Fanc40d6122017-02-22 16:21:51 +0800368 struct lpuart_fsl_reg32 *base = plat->reg;
369 u32 water;
370
371 lpuart_read32(plat->flags, &base->water, &water);
372
373 if ((water >> 24) == 0)
Jingchang Lu6209e142014-09-05 13:52:47 +0800374 return 0;
375
376 return 1;
377}
378
379/*
380 * Initialise the serial port with the given baudrate. The settings
381 * are always 8 data bits, no parity, 1 stop bit, no start bits.
382 */
Peng Fan8f5b6292018-10-19 00:26:23 +0200383static int _lpuart32_serial_init(struct udevice *dev)
Jingchang Lu6209e142014-09-05 13:52:47 +0800384{
Peng Fan8f5b6292018-10-19 00:26:23 +0200385 struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
Peng Fanc40d6122017-02-22 16:21:51 +0800386 struct lpuart_fsl_reg32 *base = (struct lpuart_fsl_reg32 *)plat->reg;
Ye Licdc16f62018-10-18 14:28:32 +0200387 u32 val, tx_fifo_size;
Jingchang Lu6209e142014-09-05 13:52:47 +0800388
Ye Licdc16f62018-10-18 14:28:32 +0200389 lpuart_read32(plat->flags, &base->ctrl, &val);
390 val &= ~CTRL_RE;
391 val &= ~CTRL_TE;
392 lpuart_write32(plat->flags, &base->ctrl, val);
Jingchang Lu6209e142014-09-05 13:52:47 +0800393
Peng Fanc40d6122017-02-22 16:21:51 +0800394 lpuart_write32(plat->flags, &base->modir, 0);
Ye Licdc16f62018-10-18 14:28:32 +0200395
396 lpuart_read32(plat->flags, &base->fifo, &val);
397 tx_fifo_size = (val & FIFO_TXSIZE_MASK) >> FIFO_TXSIZE_OFF;
398 /* Set the TX water to half of FIFO size */
399 if (tx_fifo_size > 1)
400 tx_fifo_size = tx_fifo_size >> 1;
401
402 /* Set RX water to 0, to be triggered by any receive data */
403 lpuart_write32(plat->flags, &base->water,
404 (tx_fifo_size << WATER_TXWATER_OFF));
405
406 /* Enable TX and RX FIFO */
407 val |= (FIFO_TXFE | FIFO_RXFE | FIFO_TXFLUSH | FIFO_RXFLUSH);
408 lpuart_write32(plat->flags, &base->fifo, val);
Jingchang Lu6209e142014-09-05 13:52:47 +0800409
Peng Fanc40d6122017-02-22 16:21:51 +0800410 lpuart_write32(plat->flags, &base->match, 0);
Jingchang Lu6209e142014-09-05 13:52:47 +0800411
Peng Fan126f8842018-10-18 14:28:31 +0200412 if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8) {
Peng Fan8f5b6292018-10-19 00:26:23 +0200413 _lpuart32_serial_setbrg_7ulp(dev, gd->baudrate);
Peng Fan7edf5c42017-02-22 16:21:52 +0800414 } else {
415 /* provide data bits, parity, stop bit, etc */
Peng Fan8f5b6292018-10-19 00:26:23 +0200416 _lpuart32_serial_setbrg(dev, gd->baudrate);
Peng Fan7edf5c42017-02-22 16:21:52 +0800417 }
Jingchang Lu6209e142014-09-05 13:52:47 +0800418
Peng Fanc40d6122017-02-22 16:21:51 +0800419 lpuart_write32(plat->flags, &base->ctrl, CTRL_RE | CTRL_TE);
Jingchang Lu6209e142014-09-05 13:52:47 +0800420
421 return 0;
422}
423
Peng Fanc40d6122017-02-22 16:21:51 +0800424static int lpuart_serial_setbrg(struct udevice *dev, int baudrate)
Bin Mengfdbae092016-01-13 19:39:04 -0800425{
Peng Fan8f5b6292018-10-19 00:26:23 +0200426 struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
Bin Mengfdbae092016-01-13 19:39:04 -0800427
Peng Fan7edf5c42017-02-22 16:21:52 +0800428 if (is_lpuart32(dev)) {
Peng Fan126f8842018-10-18 14:28:31 +0200429 if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8)
Peng Fan8f5b6292018-10-19 00:26:23 +0200430 _lpuart32_serial_setbrg_7ulp(dev, baudrate);
Peng Fan7edf5c42017-02-22 16:21:52 +0800431 else
Peng Fan8f5b6292018-10-19 00:26:23 +0200432 _lpuart32_serial_setbrg(dev, baudrate);
Peng Fan7edf5c42017-02-22 16:21:52 +0800433 } else {
Peng Fan8f5b6292018-10-19 00:26:23 +0200434 _lpuart_serial_setbrg(dev, baudrate);
Peng Fan7edf5c42017-02-22 16:21:52 +0800435 }
Bin Mengfdbae092016-01-13 19:39:04 -0800436
437 return 0;
438}
439
Peng Fanc40d6122017-02-22 16:21:51 +0800440static int lpuart_serial_getc(struct udevice *dev)
Bin Mengfdbae092016-01-13 19:39:04 -0800441{
442 struct lpuart_serial_platdata *plat = dev->platdata;
Bin Mengfdbae092016-01-13 19:39:04 -0800443
Peng Fanc40d6122017-02-22 16:21:51 +0800444 if (is_lpuart32(dev))
445 return _lpuart32_serial_getc(plat);
446
447 return _lpuart_serial_getc(plat);
Bin Mengfdbae092016-01-13 19:39:04 -0800448}
449
Peng Fanc40d6122017-02-22 16:21:51 +0800450static int lpuart_serial_putc(struct udevice *dev, const char c)
Bin Mengfdbae092016-01-13 19:39:04 -0800451{
452 struct lpuart_serial_platdata *plat = dev->platdata;
Bin Mengfdbae092016-01-13 19:39:04 -0800453
Peng Fanc40d6122017-02-22 16:21:51 +0800454 if (is_lpuart32(dev))
455 _lpuart32_serial_putc(plat, c);
456 else
457 _lpuart_serial_putc(plat, c);
Bin Mengfdbae092016-01-13 19:39:04 -0800458
459 return 0;
460}
461
Peng Fanc40d6122017-02-22 16:21:51 +0800462static int lpuart_serial_pending(struct udevice *dev, bool input)
Bin Mengfdbae092016-01-13 19:39:04 -0800463{
464 struct lpuart_serial_platdata *plat = dev->platdata;
465 struct lpuart_fsl *reg = plat->reg;
Peng Fanc40d6122017-02-22 16:21:51 +0800466 struct lpuart_fsl_reg32 *reg32 = plat->reg;
467 u32 stat;
468
469 if (is_lpuart32(dev)) {
470 if (input) {
471 return _lpuart32_serial_tstc(plat);
472 } else {
473 lpuart_read32(plat->flags, &reg32->stat, &stat);
474 return stat & STAT_TDRE ? 0 : 1;
475 }
476 }
Bin Mengfdbae092016-01-13 19:39:04 -0800477
478 if (input)
Peng Fanc40d6122017-02-22 16:21:51 +0800479 return _lpuart_serial_tstc(plat);
Bin Mengfdbae092016-01-13 19:39:04 -0800480 else
Peng Fanc40d6122017-02-22 16:21:51 +0800481 return __raw_readb(&reg->us1) & US1_TDRE ? 0 : 1;
Bin Mengfdbae092016-01-13 19:39:04 -0800482}
483
Peng Fanc40d6122017-02-22 16:21:51 +0800484static int lpuart_serial_probe(struct udevice *dev)
Bin Mengfdbae092016-01-13 19:39:04 -0800485{
Peng Fanc40d6122017-02-22 16:21:51 +0800486 if (is_lpuart32(dev))
Peng Fan8f5b6292018-10-19 00:26:23 +0200487 return _lpuart32_serial_init(dev);
Peng Fanc40d6122017-02-22 16:21:51 +0800488 else
Peng Fan8f5b6292018-10-19 00:26:23 +0200489 return _lpuart_serial_init(dev);
Bin Mengfdbae092016-01-13 19:39:04 -0800490}
Alison Wang427eba72013-05-27 22:55:45 +0000491
Bin Mengfdbae092016-01-13 19:39:04 -0800492static int lpuart_serial_ofdata_to_platdata(struct udevice *dev)
493{
494 struct lpuart_serial_platdata *plat = dev->platdata;
Peng Fan7edf5c42017-02-22 16:21:52 +0800495 const void *blob = gd->fdt_blob;
Simon Glassda409cc2017-05-17 17:18:09 -0600496 int node = dev_of_offset(dev);
Bin Mengfdbae092016-01-13 19:39:04 -0800497 fdt_addr_t addr;
498
Simon Glassa821c4a2017-05-17 17:18:05 -0600499 addr = devfdt_get_addr(dev);
Bin Mengfdbae092016-01-13 19:39:04 -0800500 if (addr == FDT_ADDR_T_NONE)
501 return -EINVAL;
502
Peng Fanc40d6122017-02-22 16:21:51 +0800503 plat->reg = (void *)addr;
504 plat->flags = dev_get_driver_data(dev);
Bin Mengfdbae092016-01-13 19:39:04 -0800505
Vabhav Sharma1edc5682019-01-31 12:08:10 +0000506 if (fdtdec_get_bool(blob, node, "little-endian"))
507 plat->flags &= ~LPUART_FLAG_REGMAP_ENDIAN_BIG;
508
Peng Fan7edf5c42017-02-22 16:21:52 +0800509 if (!fdt_node_check_compatible(blob, node, "fsl,ls1021a-lpuart"))
510 plat->devtype = DEV_LS1021A;
511 else if (!fdt_node_check_compatible(blob, node, "fsl,imx7ulp-lpuart"))
512 plat->devtype = DEV_MX7ULP;
513 else if (!fdt_node_check_compatible(blob, node, "fsl,vf610-lpuart"))
514 plat->devtype = DEV_VF610;
Peng Fan126f8842018-10-18 14:28:31 +0200515 else if (!fdt_node_check_compatible(blob, node, "fsl,imx8qm-lpuart"))
516 plat->devtype = DEV_IMX8;
Peng Fan7edf5c42017-02-22 16:21:52 +0800517
Bin Mengfdbae092016-01-13 19:39:04 -0800518 return 0;
519}
520
Bin Mengfdbae092016-01-13 19:39:04 -0800521static const struct dm_serial_ops lpuart_serial_ops = {
522 .putc = lpuart_serial_putc,
523 .pending = lpuart_serial_pending,
524 .getc = lpuart_serial_getc,
525 .setbrg = lpuart_serial_setbrg,
526};
527
528static const struct udevice_id lpuart_serial_ids[] = {
Peng Fanc40d6122017-02-22 16:21:51 +0800529 { .compatible = "fsl,ls1021a-lpuart", .data =
530 LPUART_FLAG_REGMAP_32BIT_REG | LPUART_FLAG_REGMAP_ENDIAN_BIG },
Peng Fan7edf5c42017-02-22 16:21:52 +0800531 { .compatible = "fsl,imx7ulp-lpuart",
532 .data = LPUART_FLAG_REGMAP_32BIT_REG },
Peng Fanc40d6122017-02-22 16:21:51 +0800533 { .compatible = "fsl,vf610-lpuart"},
Peng Fan126f8842018-10-18 14:28:31 +0200534 { .compatible = "fsl,imx8qm-lpuart",
535 .data = LPUART_FLAG_REGMAP_32BIT_REG },
Bin Mengfdbae092016-01-13 19:39:04 -0800536 { }
537};
538
539U_BOOT_DRIVER(serial_lpuart) = {
540 .name = "serial_lpuart",
541 .id = UCLASS_SERIAL,
542 .of_match = lpuart_serial_ids,
543 .ofdata_to_platdata = lpuart_serial_ofdata_to_platdata,
544 .platdata_auto_alloc_size = sizeof(struct lpuart_serial_platdata),
545 .probe = lpuart_serial_probe,
546 .ops = &lpuart_serial_ops,
Bin Mengfdbae092016-01-13 19:39:04 -0800547};