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wdenkdc7c9a12003-03-26 06:55:25 +00001/*
2 * (C) Copyright 2002
3 * Lineo, Inc. <www.lineo.com>
4 * Bernhard Kuhn <bkuhn@lineo.com>
5 *
6 * (C) Copyright 2002
7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8 * Marius Groeger <mgroeger@sysgo.de>
9 *
10 * (C) Copyright 2002
11 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
12 * Alex Zuepke <azu@sysgo.de>
13 *
14 * See file CREDITS for list of people who contributed to this
15 * project.
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 * MA 02111-1307 USA
31 */
32
33#include <common.h>
wdenk85ec0bc2003-03-31 16:34:49 +000034#include <asm/io.h>
wdenkb783eda2003-06-25 22:26:29 +000035#include <asm/arch/hardware.h>
36#include <asm/proc/ptrace.h>
wdenkdc7c9a12003-03-26 06:55:25 +000037
38extern void reset_cpu(ulong addr);
39
40/* we always count down the max. */
41#define TIMER_LOAD_VAL 0xffff
42
43/* macro to read the 16 bit timer */
44#define READ_TIMER (tmr->TC_CV)
45AT91PS_TC tmr;
46
47
wdenkdc7c9a12003-03-26 06:55:25 +000048void enable_interrupts (void)
49{
50 return;
51}
52int disable_interrupts (void)
53{
54 return 0;
55}
56
57
58void bad_mode(void)
59{
60 panic("Resetting CPU ...\n");
61 reset_cpu(0);
62}
63
64void show_regs(struct pt_regs * regs)
65{
66 unsigned long flags;
67const char *processor_modes[]=
68{ "USER_26", "FIQ_26" , "IRQ_26" , "SVC_26" , "UK4_26" , "UK5_26" , "UK6_26" , "UK7_26" ,
69 "UK8_26" , "UK9_26" , "UK10_26", "UK11_26", "UK12_26", "UK13_26", "UK14_26", "UK15_26",
70 "USER_32", "FIQ_32" , "IRQ_32" , "SVC_32" , "UK4_32" , "UK5_32" , "UK6_32" , "ABT_32" ,
71 "UK8_32" , "UK9_32" , "UK10_32", "UND_32" , "UK12_32", "UK13_32", "UK14_32", "SYS_32"
72};
73
74 flags = condition_codes(regs);
75
76 printf("pc : [<%08lx>] lr : [<%08lx>]\n"
77 "sp : %08lx ip : %08lx fp : %08lx\n",
78 instruction_pointer(regs),
79 regs->ARM_lr, regs->ARM_sp,
80 regs->ARM_ip, regs->ARM_fp);
81 printf("r10: %08lx r9 : %08lx r8 : %08lx\n",
82 regs->ARM_r10, regs->ARM_r9,
83 regs->ARM_r8);
84 printf("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
85 regs->ARM_r7, regs->ARM_r6,
86 regs->ARM_r5, regs->ARM_r4);
87 printf("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
88 regs->ARM_r3, regs->ARM_r2,
89 regs->ARM_r1, regs->ARM_r0);
90 printf("Flags: %c%c%c%c",
91 flags & CC_N_BIT ? 'N' : 'n',
92 flags & CC_Z_BIT ? 'Z' : 'z',
93 flags & CC_C_BIT ? 'C' : 'c',
94 flags & CC_V_BIT ? 'V' : 'v');
95 printf(" IRQs %s FIQs %s Mode %s%s\n",
96 interrupts_enabled(regs) ? "on" : "off",
97 fast_interrupts_enabled(regs) ? "on" : "off",
98 processor_modes[processor_mode(regs)],
99 thumb_mode(regs) ? " (T)" : "");
100}
101
102void do_undefined_instruction(struct pt_regs *pt_regs)
103{
104 printf("undefined instruction\n");
105 show_regs(pt_regs);
106 bad_mode();
107}
108
109void do_software_interrupt(struct pt_regs *pt_regs)
110{
111 printf("software interrupt\n");
112 show_regs(pt_regs);
113 bad_mode();
114}
115
116void do_prefetch_abort(struct pt_regs *pt_regs)
117{
118 printf("prefetch abort\n");
119 show_regs(pt_regs);
120 bad_mode();
121}
122
123void do_data_abort(struct pt_regs *pt_regs)
124{
125 printf("data abort\n");
126 show_regs(pt_regs);
127 bad_mode();
128}
129
130void do_not_used(struct pt_regs *pt_regs)
131{
132 printf("not used\n");
133 show_regs(pt_regs);
134 bad_mode();
135}
136
137void do_fiq(struct pt_regs *pt_regs)
138{
139 printf("fast interrupt request\n");
140 show_regs(pt_regs);
141 bad_mode();
142}
143
144void do_irq(struct pt_regs *pt_regs)
145{
146 printf("interrupt request\n");
147 show_regs(pt_regs);
148 bad_mode();
149}
150
151static ulong timestamp;
152static ulong lastinc;
153
154int interrupt_init (void)
155{
156
157 tmr = AT91C_BASE_TC0;
158
159 /* enables TC1.0 clock */
160 *AT91C_PMC_PCER = 1 << AT91C_ID_TC0; /* enable clock */
161
162 *AT91C_TCB0_BCR = 0;
163 *AT91C_TCB0_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_NONE | AT91C_TCB_TC2XC2S_NONE;
164 tmr->TC_CCR = AT91C_TC_CLKDIS;
165 tmr->TC_CMR = AT91C_TC_TIMER_DIV1_CLOCK; /* set to MCLK/2 */
166
167 tmr->TC_IDR = ~0ul;
168 tmr->TC_RC = TIMER_LOAD_VAL;
169 lastinc = TIMER_LOAD_VAL;
170 tmr->TC_CCR = AT91C_TC_SWTRG | AT91C_TC_CLKEN;
171 timestamp = 0;
172 return (0);
173}
174
175/*
176 * timer without interrupts
177 */
178
179void reset_timer(void)
180{
181 reset_timer_masked();
182}
183
184ulong get_timer (ulong base)
185{
186 return get_timer_masked() - base;
187}
188
189void set_timer (ulong t)
190{
191 timestamp = t;
192}
193
194void udelay(unsigned long usec)
195{
196 udelay_masked(usec);
197}
198
199void reset_timer_masked(void)
200{
201 /* reset time */
202 lastinc = READ_TIMER;
203 timestamp = 0;
204}
205
206ulong get_timer_masked(void)
207{
208 ulong now = READ_TIMER;
209 if (now >= lastinc)
210 {
wdenk8bde7f72003-06-27 21:31:46 +0000211 /* normal mode */
212 timestamp += now - lastinc;
wdenkdc7c9a12003-03-26 06:55:25 +0000213 } else {
wdenk8bde7f72003-06-27 21:31:46 +0000214 /* we have an overflow ... */
215 timestamp += now + TIMER_LOAD_VAL - lastinc;
wdenkdc7c9a12003-03-26 06:55:25 +0000216 }
217 lastinc = now;
218
219 return timestamp;
220}
221
222void udelay_masked(unsigned long usec)
223{
224 ulong tmo;
225
226 tmo = usec / 1000;
227 tmo *= CFG_HZ;
228 tmo /= 1000;
229
230 reset_timer_masked();
231
232 while(get_timer_masked() < tmo);
233 /*NOP*/;
234}