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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Simon Glassa8cb4fb2015-08-30 16:55:37 -06002/*
3 * Copyright (c) 2013 Google, Inc
Simon Glassa8cb4fb2015-08-30 16:55:37 -06004 */
5
6#include <common.h>
7#include <clk.h>
8#include <dm.h>
Simon Glassbfeb4432016-07-04 11:58:27 -06009#include <dt-structs.h>
Simon Glassa8cb4fb2015-08-30 16:55:37 -060010#include <dwmmc.h>
11#include <errno.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060012#include <log.h>
Simon Glassbfeb4432016-07-04 11:58:27 -060013#include <mapmem.h>
Simon Glasse1efec42016-01-21 19:43:34 -070014#include <pwrseq.h>
Simon Glassa8cb4fb2015-08-30 16:55:37 -060015#include <syscon.h>
Simon Glasse1efec42016-01-21 19:43:34 -070016#include <asm/gpio.h>
Kever Yang15f09a12019-03-28 11:01:23 +080017#include <asm/arch-rockchip/clock.h>
18#include <asm/arch-rockchip/periph.h>
Simon Glassc05ed002020-05-10 11:40:11 -060019#include <linux/delay.h>
Simon Glassa8cb4fb2015-08-30 16:55:37 -060020#include <linux/err.h>
21
Simon Glassf6e41d12016-05-14 14:03:08 -060022struct rockchip_mmc_plat {
Simon Glassbfeb4432016-07-04 11:58:27 -060023#if CONFIG_IS_ENABLED(OF_PLATDATA)
24 struct dtd_rockchip_rk3288_dw_mshc dtplat;
25#endif
Simon Glassf6e41d12016-05-14 14:03:08 -060026 struct mmc_config cfg;
27 struct mmc mmc;
28};
29
Simon Glassa8cb4fb2015-08-30 16:55:37 -060030struct rockchip_dwmmc_priv {
Stephen Warren135aa952016-06-17 09:44:00 -060031 struct clk clk;
Simon Glassa8cb4fb2015-08-30 16:55:37 -060032 struct dwmci_host host;
Simon Glass6809b042016-07-04 11:58:26 -060033 int fifo_depth;
34 bool fifo_mode;
35 u32 minmax[2];
Simon Glassa8cb4fb2015-08-30 16:55:37 -060036};
37
38static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq)
39{
40 struct udevice *dev = host->priv;
41 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
42 int ret;
43
John Keepingea0f7662023-01-17 17:07:47 +000044 /*
45 * The clock frequency chosen here affects CLKDIV in the dw_mmc core.
46 * That can be either 0 or 1, but it must be set to 1 for eMMC DDR52
47 * 8-bit mode. It will be set to 0 for all other modes.
48 */
49 if (host->mmc->selected_mode == MMC_DDR_52 && host->mmc->bus_width == 8)
50 freq *= 2;
51
Stephen Warren135aa952016-06-17 09:44:00 -060052 ret = clk_set_rate(&priv->clk, freq);
Simon Glassa8cb4fb2015-08-30 16:55:37 -060053 if (ret < 0) {
Kever Yang419b0802017-06-14 16:31:49 +080054 debug("%s: err=%d\n", __func__, ret);
Jonas Karlmand11f0da2023-03-14 00:38:32 +000055 return 0;
Simon Glassa8cb4fb2015-08-30 16:55:37 -060056 }
57
58 return freq;
59}
60
Simon Glassd1998a92020-12-03 16:55:21 -070061static int rockchip_dwmmc_of_to_plat(struct udevice *dev)
Simon Glassa8cb4fb2015-08-30 16:55:37 -060062{
63 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
64 struct dwmci_host *host = &priv->host;
65
Simon Glassdcfc42b2021-08-07 07:24:06 -060066 if (!CONFIG_IS_ENABLED(OF_REAL))
67 return 0;
68
Simon Glassa8cb4fb2015-08-30 16:55:37 -060069 host->name = dev->name;
Philipp Tomsichbe5f04e2017-09-11 22:04:15 +020070 host->ioaddr = dev_read_addr_ptr(dev);
Philipp Tomsichfd1bf8d2017-06-07 18:46:00 +020071 host->buswidth = dev_read_u32_default(dev, "bus-width", 4);
Simon Glassa8cb4fb2015-08-30 16:55:37 -060072 host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
73 host->priv = dev;
74
huang linace21982015-11-18 09:37:25 +080075 /* use non-removeable as sdcard and emmc as judgement */
Philipp Tomsichfd1bf8d2017-06-07 18:46:00 +020076 if (dev_read_bool(dev, "non-removable"))
huang lin65793852016-01-08 14:06:49 +080077 host->dev_index = 0;
78 else
huang linace21982015-11-18 09:37:25 +080079 host->dev_index = 1;
Simon Glassa8cb4fb2015-08-30 16:55:37 -060080
Philipp Tomsichfd1bf8d2017-06-07 18:46:00 +020081 priv->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0);
82
Simon Glass6809b042016-07-04 11:58:26 -060083 if (priv->fifo_depth < 0)
84 return -EINVAL;
Philipp Tomsichfd1bf8d2017-06-07 18:46:00 +020085 priv->fifo_mode = dev_read_bool(dev, "fifo-mode");
Philipp Tomsichff71f9a2017-04-25 09:52:07 +020086
Heiko Stuebnerc8dd0e42019-11-19 12:04:01 +010087#ifdef CONFIG_SPL_BUILD
88 if (!priv->fifo_mode)
89 priv->fifo_mode = dev_read_bool(dev, "u-boot,spl-fifo-mode");
90#endif
91
Philipp Tomsichff71f9a2017-04-25 09:52:07 +020092 /*
93 * 'clock-freq-min-max' is deprecated
94 * (see https://github.com/torvalds/linux/commit/b023030f10573de738bbe8df63d43acab64c9f7b)
95 */
Philipp Tomsichfd1bf8d2017-06-07 18:46:00 +020096 if (dev_read_u32_array(dev, "clock-freq-min-max", priv->minmax, 2)) {
97 int val = dev_read_u32_default(dev, "max-frequency", -EINVAL);
Philipp Tomsichff71f9a2017-04-25 09:52:07 +020098
99 if (val < 0)
100 return val;
101
102 priv->minmax[0] = 400000; /* 400 kHz */
103 priv->minmax[1] = val;
104 } else {
105 debug("%s: 'clock-freq-min-max' property was deprecated.\n",
106 __func__);
107 }
Simon Glassdcfc42b2021-08-07 07:24:06 -0600108
Simon Glassa8cb4fb2015-08-30 16:55:37 -0600109 return 0;
110}
111
112static int rockchip_dwmmc_probe(struct udevice *dev)
113{
Simon Glassc69cda22020-12-03 16:55:20 -0700114 struct rockchip_mmc_plat *plat = dev_get_plat(dev);
Simon Glassa8cb4fb2015-08-30 16:55:37 -0600115 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
116 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
117 struct dwmci_host *host = &priv->host;
Simon Glassa8cb4fb2015-08-30 16:55:37 -0600118 int ret;
119
Simon Glassbfeb4432016-07-04 11:58:27 -0600120#if CONFIG_IS_ENABLED(OF_PLATDATA)
121 struct dtd_rockchip_rk3288_dw_mshc *dtplat = &plat->dtplat;
122
123 host->name = dev->name;
124 host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
125 host->buswidth = dtplat->bus_width;
126 host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
127 host->priv = dev;
128 host->dev_index = 0;
129 priv->fifo_depth = dtplat->fifo_depth;
Johan Jonker2d3bb402022-04-09 18:55:09 +0200130 priv->fifo_mode = dtplat->u_boot_spl_fifo_mode;
Kever Yang80935292017-06-14 16:31:46 +0800131 priv->minmax[0] = 400000; /* 400 kHz */
132 priv->minmax[1] = dtplat->max_frequency;
Simon Glassbfeb4432016-07-04 11:58:27 -0600133
Johan Jonker9d75daf2022-04-09 18:55:08 +0200134 ret = clk_get_by_phandle(dev, &dtplat->clocks[1], &priv->clk);
Simon Glassbfeb4432016-07-04 11:58:27 -0600135 if (ret < 0)
136 return ret;
137#else
Johan Jonker9d75daf2022-04-09 18:55:08 +0200138 ret = clk_get_by_index(dev, 1, &priv->clk);
Simon Glass898d6432016-01-21 19:43:38 -0700139 if (ret < 0)
Simon Glassa8cb4fb2015-08-30 16:55:37 -0600140 return ret;
Simon Glassbfeb4432016-07-04 11:58:27 -0600141#endif
huang lin28637242015-11-17 14:20:24 +0800142 host->fifoth_val = MSIZE(0x2) |
Simon Glass6809b042016-07-04 11:58:26 -0600143 RX_WMARK(priv->fifo_depth / 2 - 1) |
144 TX_WMARK(priv->fifo_depth / 2);
huang lin28637242015-11-17 14:20:24 +0800145
Simon Glass6809b042016-07-04 11:58:26 -0600146 host->fifo_mode = priv->fifo_mode;
huang lin28637242015-11-17 14:20:24 +0800147
Jaehoon Chung9d7e6612021-02-16 10:16:54 +0900148#ifdef CONFIG_MMC_PWRSEQ
Simon Glasse1efec42016-01-21 19:43:34 -0700149 /* Enable power if needed */
Jaehoon Chung9d7e6612021-02-16 10:16:54 +0900150 ret = mmc_pwrseq_get_power(dev, &plat->cfg);
Simon Glasse1efec42016-01-21 19:43:34 -0700151 if (!ret) {
Jaehoon Chung9d7e6612021-02-16 10:16:54 +0900152 ret = pwrseq_set_power(plat->cfg.pwr_dev, true);
Simon Glasse1efec42016-01-21 19:43:34 -0700153 if (ret)
154 return ret;
155 }
156#endif
Jaehoon Chunge5113c32016-09-23 19:13:16 +0900157 dwmci_setup_cfg(&plat->cfg, host, priv->minmax[1], priv->minmax[0]);
Simon Glassf6e41d12016-05-14 14:03:08 -0600158 host->mmc = &plat->mmc;
Simon Glassf6e41d12016-05-14 14:03:08 -0600159 host->mmc->priv = &priv->host;
Simon Glasscffe5d82016-05-01 13:52:34 -0600160 host->mmc->dev = dev;
Simon Glassa8cb4fb2015-08-30 16:55:37 -0600161 upriv->mmc = host->mmc;
162
Simon Glass42b37d82016-06-12 23:30:24 -0600163 return dwmci_probe(dev);
Simon Glassa8cb4fb2015-08-30 16:55:37 -0600164}
165
Simon Glassf6e41d12016-05-14 14:03:08 -0600166static int rockchip_dwmmc_bind(struct udevice *dev)
167{
Simon Glassc69cda22020-12-03 16:55:20 -0700168 struct rockchip_mmc_plat *plat = dev_get_plat(dev);
Simon Glassf6e41d12016-05-14 14:03:08 -0600169
Masahiro Yamada24f5aec2016-09-06 22:17:32 +0900170 return dwmci_bind(dev, &plat->mmc, &plat->cfg);
Simon Glassf6e41d12016-05-14 14:03:08 -0600171}
172
Simon Glassa8cb4fb2015-08-30 16:55:37 -0600173static const struct udevice_id rockchip_dwmmc_ids[] = {
Heiko Stuebner26a52f32018-09-21 10:59:46 +0200174 { .compatible = "rockchip,rk2928-dw-mshc" },
Simon Glassa8cb4fb2015-08-30 16:55:37 -0600175 { .compatible = "rockchip,rk3288-dw-mshc" },
176 { }
177};
178
Walter Lozanoe3e24702020-06-25 01:10:04 -0300179U_BOOT_DRIVER(rockchip_rk3288_dw_mshc) = {
Simon Glassbfeb4432016-07-04 11:58:27 -0600180 .name = "rockchip_rk3288_dw_mshc",
Simon Glassa8cb4fb2015-08-30 16:55:37 -0600181 .id = UCLASS_MMC,
182 .of_match = rockchip_dwmmc_ids,
Simon Glassd1998a92020-12-03 16:55:21 -0700183 .of_to_plat = rockchip_dwmmc_of_to_plat,
Simon Glass42b37d82016-06-12 23:30:24 -0600184 .ops = &dm_dwmci_ops,
Simon Glassf6e41d12016-05-14 14:03:08 -0600185 .bind = rockchip_dwmmc_bind,
Simon Glassa8cb4fb2015-08-30 16:55:37 -0600186 .probe = rockchip_dwmmc_probe,
Simon Glass41575d82020-12-03 16:55:17 -0700187 .priv_auto = sizeof(struct rockchip_dwmmc_priv),
Simon Glasscaa4daa2020-12-03 16:55:18 -0700188 .plat_auto = sizeof(struct rockchip_mmc_plat),
Simon Glassa8cb4fb2015-08-30 16:55:37 -0600189};
Simon Glasse1efec42016-01-21 19:43:34 -0700190
Johan Jonker2d3bb402022-04-09 18:55:09 +0200191DM_DRIVER_ALIAS(rockchip_rk3288_dw_mshc, rockchip_rk2928_dw_mshc)
Simon Glassbdf8fd72020-12-28 20:34:57 -0700192DM_DRIVER_ALIAS(rockchip_rk3288_dw_mshc, rockchip_rk3328_dw_mshc)
193DM_DRIVER_ALIAS(rockchip_rk3288_dw_mshc, rockchip_rk3368_dw_mshc)