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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 8c3019216edd18297527c3c0926c319eca2a43f5 / . / arch / arm / dts / ast2600.dtsi
blob: ef5b131ac0afb325e4dfc3b492ac63c2233cf7d4 [file] [log] [blame]
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2#include <dt-bindings/interrupt-controller/arm-gic.h>
3#include "skeleton.dtsi"
4
5/ {
6 model = "Aspeed BMC";
7 compatible = "aspeed,ast2600";
8 #address-cells = <1>;
9 #size-cells = <1>;
10 interrupt-parent = <&gic>;
11
12 aliases {
13 i2c0 = &i2c0;
14 i2c1 = &i2c1;
15 i2c2 = &i2c2;
16 i2c3 = &i2c3;
17 i2c4 = &i2c4;
18 i2c5 = &i2c5;
19 i2c6 = &i2c6;
20 i2c7 = &i2c7;
21 i2c8 = &i2c8;
22 i2c9 = &i2c9;
23 i2c10 = &i2c10;
24 i2c11 = &i2c11;
25 i2c12 = &i2c12;
26 i2c13 = &i2c13;
27 i2c14 = &i2c14;
28 i2c15 = &i2c15;
29 serial0 = &uart1;
30 serial1 = &uart2;
31 serial2 = &uart3;
32 serial3 = &uart4;
33 serial4 = &uart5;
34 serial5 = &uart6;
35 serial6 = &uart7;
36 serial7 = &uart8;
37 serial8 = &uart9;
38 serial9 = &uart10;
39 serial10 = &uart11;
40 serial11 = &uart12;
41 serial12 = &uart13;
42 };
43
44 cpus {
45 #address-cells = <1>;
46 #size-cells = <0>;
47 enable-method = "aspeed,ast2600-smp";
48
49 cpu@0 {
50 compatible = "arm,cortex-a7";
51 device_type = "cpu";
52 reg = <0xf00>;
53 };
54
55 cpu@1 {
56 compatible = "arm,cortex-a7";
57 device_type = "cpu";
58 reg = <0xf01>;
59 };
60
61 };
62
63 timer {
64 compatible = "arm,armv7-timer";
65 interrupt-parent = <&gic>;
66 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
67 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
68 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
69 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
70 };
71
72 reserved-memory {
73 #address-cells = <1>;
74 #size-cells = <1>;
75 ranges;
76
77 gfx_memory: framebuffer {
78 size = <0x01000000>;
79 alignment = <0x01000000>;
80 compatible = "shared-dma-pool";
81 reusable;
82 };
83
84 video_memory: video {
85 size = <0x04000000>;
86 alignment = <0x01000000>;
87 compatible = "shared-dma-pool";
88 no-map;
89 };
90 };
91
92 ahb {
93 compatible = "simple-bus";
94 #address-cells = <1>;
95 #size-cells = <1>;
96 device_type = "soc";
97 ranges;
98
99 gic: interrupt-controller@40461000 {
100 compatible = "arm,cortex-a7-gic";
101 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
102 #interrupt-cells = <3>;
103 interrupt-controller;
104 interrupt-parent = <&gic>;
105 reg = <0x40461000 0x1000>,
106 <0x40462000 0x1000>,
107 <0x40464000 0x2000>,
108 <0x40466000 0x2000>;
109 };
110
111 ahbc: ahbc@1e600000 {
112 compatible = "aspeed,aspeed-ahbc";
113 reg = < 0x1e600000 0x100>;
114 };
115
Billy Tsai5b66ebb2022-03-08 11:04:07 +0800[diff] [blame]116 pwm_tach: pwm_tach@1e610000 {
117 compatible = "aspeed,ast2600-pwm-tach", "simple-mfd", "syscon";
118 reg = <0x1e610000 0x100>;
119 clocks = <&scu ASPEED_CLK_AHB>;
120 resets = <&rst ASPEED_RESET_PWM>;
121
122 pwm: pwm {
123 compatible = "aspeed,ast2600-pwm";
124 #pwm-cells = <3>;
125 #address-cells = <1>;
126 #size-cells = <0>;
127 status = "disabled";
128 };
129 };
130
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]131 fmc: flash-controller@1e620000 {
132 reg = < 0x1e620000 0xc4
133 0x20000000 0x10000000 >;
134 #address-cells = <1>;
135 #size-cells = <0>;
136 compatible = "aspeed,ast2600-fmc";
137 status = "disabled";
138 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
139 clocks = <&scu ASPEED_CLK_AHB>;
140 num-cs = <3>;
141 flash@0 {
142 reg = < 0 >;
143 compatible = "jedec,spi-nor";
144 status = "disabled";
145 };
146 flash@1 {
147 reg = < 1 >;
148 compatible = "jedec,spi-nor";
149 status = "disabled";
150 };
151 flash@2 {
152 reg = < 2 >;
153 compatible = "jedec,spi-nor";
154 status = "disabled";
155 };
156 };
157
158 spi1: flash-controller@1e630000 {
159 reg = < 0x1e630000 0xc4
160 0x30000000 0x08000000 >;
161 #address-cells = <1>;
162 #size-cells = <0>;
163 compatible = "aspeed,ast2600-spi";
164 clocks = <&scu ASPEED_CLK_AHB>;
165 num-cs = <2>;
166 status = "disabled";
167 flash@0 {
168 reg = < 0 >;
169 compatible = "jedec,spi-nor";
170 status = "disabled";
171 };
172 flash@1 {
173 reg = < 1 >;
174 compatible = "jedec,spi-nor";
175 status = "disabled";
176 };
177 };
178
179 spi2: flash-controller@1e631000 {
180 reg = < 0x1e631000 0xc4
181 0x50000000 0x08000000 >;
182 #address-cells = <1>;
183 #size-cells = <0>;
184 compatible = "aspeed,ast2600-spi";
185 clocks = <&scu ASPEED_CLK_AHB>;
186 num-cs = <3>;
187 status = "disabled";
188 flash@0 {
189 reg = < 0 >;
190 compatible = "jedec,spi-nor";
191 status = "disabled";
192 };
193 flash@1 {
194 reg = < 1 >;
195 compatible = "jedec,spi-nor";
196 status = "disabled";
197 };
198 flash@2 {
199 reg = < 2 >;
200 compatible = "jedec,spi-nor";
201 status = "disabled";
202 };
203 };
204
Joel Stanleya2f16d02021-10-27 14:17:28 +0800[diff] [blame]205 hace: hace@1e6d0000 {
206 compatible = "aspeed,ast2600-hace";
207 reg = <0x1e6d0000 0x200>;
208 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
209 clocks = <&scu ASPEED_CLK_GATE_YCLK>;
210 status = "disabled";
211 };
212
Chia-Wei Wangf0552272021-10-27 14:17:31 +0800[diff] [blame]213 acry: acry@1e6fa000 {
214 compatible = "aspeed,ast2600-acry";
215 reg = <0x1e6fa000 0x1000>,
216 <0x1e710000 0x10000>;
217 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&scu ASPEED_CLK_GATE_RSACLK>;
219 status = "disabled";
220 };
221
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]222 edac: sdram@1e6e0000 {
223 compatible = "aspeed,ast2600-sdram-edac";
224 reg = <0x1e6e0000 0x174>;
225 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
226 };
227
Dylan Hungabc75892021-12-09 10:12:26 +0800[diff] [blame]228 mdio: bus@1e650000 {
229 compatible = "simple-bus";
230 #address-cells = <1>;
231 #size-cells = <1>;
232 ranges = <0 0x1e650000 0x100>;
233
234 mdio0: mdio@0 {
235 compatible = "aspeed,ast2600-mdio";
236 reg = <0 0x8>;
237 resets = <&rst ASPEED_RESET_MII>;
238 pinctrl-names = "default";
239 pinctrl-0 = <&pinctrl_mdio1_default>;
240 status = "disabled";
241 };
242
243 mdio1: mdio@8 {
244 compatible = "aspeed,ast2600-mdio";
245 reg = <0x8 0x8>;
246 resets = <&rst ASPEED_RESET_MII>;
247 pinctrl-names = "default";
248 pinctrl-0 = <&pinctrl_mdio2_default>;
249 status = "disabled";
250 };
251
252 mdio2: mdio@10 {
253 compatible = "aspeed,ast2600-mdio";
254 reg = <0x10 0x8>;
255 resets = <&rst ASPEED_RESET_MII>;
256 pinctrl-names = "default";
257 pinctrl-0 = <&pinctrl_mdio3_default>;
258 status = "disabled";
259 };
260
261 mdio3: mdio@18 {
262 compatible = "aspeed,ast2600-mdio";
263 reg = <0x18 0x8>;
264 resets = <&rst ASPEED_RESET_MII>;
265 pinctrl-names = "default";
266 pinctrl-0 = <&pinctrl_mdio4_default>;
267 status = "disabled";
268 };
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]269 };
270
271 mac0: ftgmac@1e660000 {
272 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
273 reg = <0x1e660000 0x180>, <0x1e650000 0x4>;
274 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
275 clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>;
276 status = "disabled";
277 };
278
279 mac1: ftgmac@1e680000 {
280 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
281 reg = <0x1e680000 0x180>, <0x1e650008 0x4>;
282 #address-cells = <1>;
283 #size-cells = <0>;
284 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&scu ASPEED_CLK_GATE_MAC2CLK>;
286 status = "disabled";
287 };
288
289 mac2: ftgmac@1e670000 {
290 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
291 reg = <0x1e670000 0x180>, <0x1e650010 0x4>;
292 #address-cells = <1>;
293 #size-cells = <0>;
294 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&scu ASPEED_CLK_GATE_MAC3CLK>;
296 status = "disabled";
297 };
298
299 mac3: ftgmac@1e690000 {
300 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
301 reg = <0x1e690000 0x180>, <0x1e650018 0x4>;
302 #address-cells = <1>;
303 #size-cells = <0>;
304 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
305 clocks = <&scu ASPEED_CLK_GATE_MAC4CLK>;
306 status = "disabled";
307 };
308
309 ehci0: usb@1e6a1000 {
310 compatible = "aspeed,aspeed-ehci", "usb-ehci";
311 reg = <0x1e6a1000 0x100>;
312 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&scu ASPEED_CLK_GATE_USBPORT1CLK>;
314 pinctrl-names = "default";
315 pinctrl-0 = <&pinctrl_usb2ah_default>;
316 status = "disabled";
317 };
318
319 ehci1: usb@1e6a3000 {
320 compatible = "aspeed,aspeed-ehci", "usb-ehci";
321 reg = <0x1e6a3000 0x100>;
322 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
323 clocks = <&scu ASPEED_CLK_GATE_USBPORT2CLK>;
324 pinctrl-names = "default";
325 pinctrl-0 = <&pinctrl_usb2bh_default>;
326 status = "disabled";
327 };
328
329 apb {
330 compatible = "simple-bus";
331 #address-cells = <1>;
332 #size-cells = <1>;
333 ranges;
334
335 syscon: syscon@1e6e2000 {
336 compatible = "aspeed,g6-scu", "syscon", "simple-mfd";
337 reg = <0x1e6e2000 0x1000>;
338 #address-cells = <1>;
339 #size-cells = <1>;
340 #clock-cells = <1>;
341 #reset-cells = <1>;
342 ranges = <0 0x1e6e2000 0x1000>;
343
344 pinctrl: pinctrl {
345 compatible = "aspeed,g6-pinctrl";
346 aspeed,external-nodes = <&gfx &lhc>;
347
348 };
349
350 vga_scratch: scratch {
351 compatible = "aspeed,bmc-misc";
352 };
353
354 scu_ic0: interrupt-controller@0 {
355 #interrupt-cells = <1>;
356 compatible = "aspeed,ast2600-scu-ic";
357 reg = <0x560 0x10>;
358 interrupt-parent = <&gic>;
359 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
360 interrupt-controller;
361 };
362
363 scu_ic1: interrupt-controller@1 {
364 #interrupt-cells = <1>;
365 compatible = "aspeed,ast2600-scu-ic";
366 reg = <0x570 0x10>;
367 interrupt-parent = <&gic>;
368 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
369 interrupt-controller;
370 };
371
372 };
373
374 smp-memram@0 {
375 compatible = "aspeed,ast2600-smpmem", "syscon";
376 reg = <0x1e6e2180 0x40>;
377 };
378
379 gfx: display@1e6e6000 {
380 compatible = "aspeed,ast2500-gfx", "syscon";
381 reg = <0x1e6e6000 0x1000>;
382 reg-io-width = <4>;
383 };
384
385 pcie_bridge0: pcie@1e6ed000 {
386 compatible = "aspeed,ast2600-pcie";
387 #address-cells = <3>;
388 #size-cells = <2>;
389 reg = <0x1e6ed000 0x100>;
390 ranges = <0x81000000 0x0 0x0 0x0 0x0 0x10000>,
391 <0x82000000 0x0 0x60000000 0x60000000 0x0 0x10000000>;
392 device_type = "pci";
393 bus-range = <0x00 0xff>;
394 resets = <&rst ASPEED_RESET_PCIE_DEV_O>;
395 cfg-handle = <&pcie_cfg0>;
396 pinctrl-names = "default";
397 pinctrl-0 = <&pinctrl_pcie0rc_default>;
398
399 status = "disabled";
400 };
401
402 pcie_bridge1: pcie@1e6ed200 {
403 compatible = "aspeed,ast2600-pcie";
404 #address-cells = <3>;
405 #size-cells = <2>;
406 reg = <0x1e6ed200 0x100>;
407 ranges = <0x81000000 0x0 0x0 0x10000 0x00 0x10000>,
408 <0x82000000 0x0 0x70000000 0x70000000 0x0 0x10000000>;
409 device_type = "pci";
410 bus-range = <0x00 0xff>;
411 resets = <&rst ASPEED_RESET_PCIE_RC_O>;
412 cfg-handle = <&pcie_cfg1>;
413 pinctrl-names = "default";
414 pinctrl-0 = <&pinctrl_pcie1rc_default>;
415
416 status = "disabled";
417 };
418
419 sdhci: sdhci@1e740000 {
420 #interrupt-cells = <1>;
421 compatible = "aspeed,aspeed-sdhci-irq", "simple-mfd";
422 reg = <0x1e740000 0x1000>;
423 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
424 interrupt-controller;
425 clocks = <&scu ASPEED_CLK_GATE_SDCLK>,
426 <&scu ASPEED_CLK_GATE_SDEXTCLK>;
427 clock-names = "ctrlclk", "extclk";
428 #address-cells = <1>;
429 #size-cells = <1>;
430 ranges = <0x0 0x1e740000 0x1000>;
431
432 sdhci_slot0: sdhci_slot0@100 {
433 compatible = "aspeed,sdhci-ast2600";
434 reg = <0x100 0x100>;
435 interrupts = <0>;
436 interrupt-parent = <&sdhci>;
437 sdhci,auto-cmd12;
438 clocks = <&scu ASPEED_CLK_SDIO>;
439 status = "disabled";
440 };
441
442 sdhci_slot1: sdhci_slot1@200 {
443 compatible = "aspeed,sdhci-ast2600";
444 reg = <0x200 0x100>;
445 interrupts = <1>;
446 interrupt-parent = <&sdhci>;
447 sdhci,auto-cmd12;
448 clocks = <&scu ASPEED_CLK_SDIO>;
449 status = "disabled";
450 };
451 };
452
453 emmc: emmc@1e750000 {
454 #interrupt-cells = <1>;
455 compatible = "aspeed,aspeed-emmc-irq", "simple-mfd";
456 reg = <0x1e750000 0x1000>;
457 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
458 interrupt-controller;
459 clocks = <&scu ASPEED_CLK_GATE_EMMCCLK>,
460 <&scu ASPEED_CLK_GATE_EMMCEXTCLK>;
461 clock-names = "ctrlclk", "extclk";
462 #address-cells = <1>;
463 #size-cells = <1>;
464 ranges = <0x0 0x1e750000 0x1000>;
465
466 emmc_slot0: emmc_slot0@100 {
467 compatible = "aspeed,emmc-ast2600";
468 reg = <0x100 0x100>;
469 interrupts = <0>;
470 interrupt-parent = <&emmc>;
471 clocks = <&scu ASPEED_CLK_EMMC>;
472 status = "disabled";
473 };
474 };
475
476 h2x: h2x@1e770000 {
477 compatible = "aspeed,ast2600-h2x";
478 reg = <0x1e770000 0x100>;
479 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
480 resets = <&rst ASPEED_RESET_H2X>;
481 #address-cells = <1>;
482 #size-cells = <1>;
483 ranges = <0x0 0x1e770000 0x100>;
484
485 status = "disabled";
486
487 pcie_cfg0: cfg0@80 {
488 reg = <0x80 0x80>;
489 compatible = "aspeed,ast2600-pcie-cfg";
490 };
491
492 pcie_cfg1: cfg1@C0 {
493 compatible = "aspeed,ast2600-pcie-cfg";
494 reg = <0xC0 0x80>;
495 };
496 };
497
498 gpio0: gpio@1e780000 {
499 compatible = "aspeed,ast2600-gpio";
500 reg = <0x1e780000 0x1000>;
501 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
502 #gpio-cells = <2>;
503 gpio-controller;
504 interrupt-controller;
505 gpio-ranges = <&pinctrl 0 0 220>;
506 ngpios = <208>;
507 };
508
509 gpio1: gpio@1e780800 {
510 compatible = "aspeed,ast2600-gpio";
511 reg = <0x1e780800 0x800>;
512 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
513 #gpio-cells = <2>;
514 gpio-controller;
515 interrupt-controller;
516 gpio-ranges = <&pinctrl 0 0 208>;
517 ngpios = <36>;
518 };
519
520 uart1: serial@1e783000 {
521 compatible = "ns16550a";
522 reg = <0x1e783000 0x20>;
523 reg-shift = <2>;
524 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&scu ASPEED_CLK_GATE_UART1CLK>;
526 clock-frequency = <1846154>;
527 no-loopback-test;
528 status = "disabled";
529 };
530
531 uart5: serial@1e784000 {
532 compatible = "ns16550a";
533 reg = <0x1e784000 0x1000>;
534 reg-shift = <2>;
535 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
536 clocks = <&scu ASPEED_CLK_GATE_UART5CLK>;
537 clock-frequency = <1846154>;
538 no-loopback-test;
539 status = "disabled";
540 };
541
542 wdt1: watchdog@1e785000 {
543 compatible = "aspeed,ast2600-wdt";
544 reg = <0x1e785000 0x40>;
Chia-Wei Wang8e1ebdc2021-09-16 14:10:09 +0800[diff] [blame]545 status = "disabled";
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]546 };
547
548 wdt2: watchdog@1e785040 {
549 compatible = "aspeed,ast2600-wdt";
550 reg = <0x1e785040 0x40>;
Chia-Wei Wang8e1ebdc2021-09-16 14:10:09 +0800[diff] [blame]551 status = "disabled";
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]552 };
553
554 wdt3: watchdog@1e785080 {
555 compatible = "aspeed,ast2600-wdt";
556 reg = <0x1e785080 0x40>;
Chia-Wei Wang8e1ebdc2021-09-16 14:10:09 +0800[diff] [blame]557 status = "disabled";
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]558 };
559
560 wdt4: watchdog@1e7850C0 {
561 compatible = "aspeed,ast2600-wdt";
562 reg = <0x1e7850C0 0x40>;
Chia-Wei Wang8e1ebdc2021-09-16 14:10:09 +0800[diff] [blame]563 status = "disabled";
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]564 };
565
566 lpc: lpc@1e789000 {
567 compatible = "aspeed,ast2600-lpc", "simple-mfd", "syscon";
568 reg = <0x1e789000 0x1000>;
569
570 #address-cells = <1>;
571 #size-cells = <1>;
572 ranges = <0x0 0x1e789000 0x1000>;
573
574 kcs1: kcs1@0 {
575 compatible = "aspeed,ast2600-kcs-bmc";
576 reg = <0x0 0x80>;
577 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
578 kcs_chan = <1>;
579 kcs_addr = <0xCA0>;
580 status = "disabled";
581 };
582
583 kcs2: kcs2@0 {
584 compatible = "aspeed,ast2600-kcs-bmc";
585 reg = <0x0 0x80>;
586 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
587 kcs_chan = <2>;
588 kcs_addr = <0xCA8>;
589 status = "disabled";
590 };
591
592 kcs3: kcs3@0 {
593 compatible = "aspeed,ast2600-kcs-bmc";
594 reg = <0x0 0x80>;
595 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
596 kcs_chan = <3>;
597 kcs_addr = <0xCA2>;
598 };
599
600 kcs4: kcs4@0 {
601 compatible = "aspeed,ast2600-kcs-bmc";
602 reg = <0x0 0x120>;
603 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
604 kcs_chan = <4>;
605 kcs_addr = <0xCA4>;
606 status = "disabled";
607 };
608
609 lpc_ctrl: lpc-ctrl@80 {
610 compatible = "aspeed,ast2600-lpc-ctrl";
611 reg = <0x80 0x80>;
612 status = "disabled";
613 };
614
615 lpc_snoop: lpc-snoop@80 {
616 compatible = "aspeed,ast2600-lpc-snoop";
617 reg = <0x80 0x80>;
618 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
619 status = "disabled";
620 };
621
622 lhc: lhc@a0 {
623 compatible = "aspeed,ast2600-lhc";
624 reg = <0xa0 0x24 0xc8 0x8>;
625 };
626
627 lpc_reset: reset-controller@98 {
628 compatible = "aspeed,ast2600-lpc-reset";
629 reg = <0x98 0x4>;
630 #reset-cells = <1>;
631 status = "disabled";
632 };
633
634 ibt: ibt@140 {
635 compatible = "aspeed,ast2600-ibt-bmc";
636 reg = <0x140 0x18>;
637 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
638 status = "disabled";
639 };
640
641 sio_regs: regs {
642 compatible = "aspeed,bmc-misc";
643 };
644
645 mbox: mbox@200 {
646 compatible = "aspeed,ast2600-mbox";
647 reg = <0x200 0x5c>;
648 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
649 #mbox-cells = <1>;
650 status = "disabled";
651 };
652 };
653
654 uart2: serial@1e78d000 {
655 compatible = "ns16550a";
656 reg = <0x1e78d000 0x20>;
657 reg-shift = <2>;
658 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
659 clocks = <&scu ASPEED_CLK_GATE_UART2CLK>;
660 clock-frequency = <1846154>;
661 no-loopback-test;
662 status = "disabled";
663 };
664
665 uart3: serial@1e78e000 {
666 compatible = "ns16550a";
667 reg = <0x1e78e000 0x20>;
668 reg-shift = <2>;
669 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
670 clocks = <&scu ASPEED_CLK_GATE_UART3CLK>;
671 clock-frequency = <1846154>;
672 no-loopback-test;
673 status = "disabled";
674 };
675
676 uart4: serial@1e78f000 {
677 compatible = "ns16550a";
678 reg = <0x1e78f000 0x20>;
679 reg-shift = <2>;
680 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
681 clocks = <&scu ASPEED_CLK_GATE_UART4CLK>;
682 clock-frequency = <1846154>;
683 no-loopback-test;
684 status = "disabled";
685 };
686
687 i2c: bus@1e78a000 {
688 compatible = "simple-bus";
689 #address-cells = <1>;
690 #size-cells = <1>;
691 ranges = <0 0x1e78a000 0x1000>;
692 };
693
694 fsim0: fsi@1e79b000 {
695 compatible = "aspeed,ast2600-fsi-master", "fsi-master";
696 reg = <0x1e79b000 0x94>;
697 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
698 pinctrl-names = "default";
699 pinctrl-0 = <&pinctrl_fsi1_default>;
700 clocks = <&scu ASPEED_CLK_GATE_FSICLK>;
701 status = "disabled";
702 };
703
704 fsim1: fsi@1e79b100 {
705 compatible = "aspeed,ast2600-fsi-master", "fsi-master";
706 reg = <0x1e79b100 0x94>;
707 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
708 pinctrl-names = "default";
709 pinctrl-0 = <&pinctrl_fsi2_default>;
710 clocks = <&scu ASPEED_CLK_GATE_FSICLK>;
711 status = "disabled";
712 };
713
714 uart6: serial@1e790000 {
715 compatible = "ns16550a";
716 reg = <0x1e790000 0x20>;
717 reg-shift = <2>;
718 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
719 clocks = <&scu ASPEED_CLK_GATE_UART6CLK>;
720 clock-frequency = <1846154>;
721 no-loopback-test;
722 status = "disabled";
723 };
724
725 uart7: serial@1e790100 {
726 compatible = "ns16550a";
727 reg = <0x1e790100 0x20>;
728 reg-shift = <2>;
729 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
730 clocks = <&scu ASPEED_CLK_GATE_UART7CLK>;
731 clock-frequency = <1846154>;
732 no-loopback-test;
733 status = "disabled";
734 };
735
736 uart8: serial@1e790200 {
737 compatible = "ns16550a";
738 reg = <0x1e790200 0x20>;
739 reg-shift = <2>;
740 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
741 clocks = <&scu ASPEED_CLK_GATE_UART8CLK>;
742 clock-frequency = <1846154>;
743 no-loopback-test;
744 status = "disabled";
745 };
746
747 uart9: serial@1e790300 {
748 compatible = "ns16550a";
749 reg = <0x1e790300 0x20>;
750 reg-shift = <2>;
751 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
752 clocks = <&scu ASPEED_CLK_GATE_UART9CLK>;
753 clock-frequency = <1846154>;
754 no-loopback-test;
755 status = "disabled";
756 };
757
758 uart10: serial@1e790400 {
759 compatible = "ns16550a";
760 reg = <0x1e790400 0x20>;
761 reg-shift = <2>;
762 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
763 clocks = <&scu ASPEED_CLK_GATE_UART10CLK>;
764 clock-frequency = <1846154>;
765 no-loopback-test;
766 status = "disabled";
767 };
768
769 uart11: serial@1e790500 {
770 compatible = "ns16550a";
771 reg = <0x1e790400 0x20>;
772 reg-shift = <2>;
773 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
774 clocks = <&scu ASPEED_CLK_GATE_UART11CLK>;
775 clock-frequency = <1846154>;
776 no-loopback-test;
777 status = "disabled";
778 };
779
780 uart12: serial@1e790600 {
781 compatible = "ns16550a";
782 reg = <0x1e790600 0x20>;
783 reg-shift = <2>;
784 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
785 clocks = <&scu ASPEED_CLK_GATE_UART12CLK>;
786 clock-frequency = <1846154>;
787 no-loopback-test;
788 status = "disabled";
789 };
790
791 uart13: serial@1e790700 {
792 compatible = "ns16550a";
793 reg = <0x1e790700 0x20>;
794 reg-shift = <2>;
795 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
796 clocks = <&scu ASPEED_CLK_GATE_UART13CLK>;
797 clock-frequency = <1846154>;
798 no-loopback-test;
799 status = "disabled";
800 };
801
802 display_port: dp@1e6eb000 {
803 compatible = "aspeed,ast2600-displayport";
804 reg = <0x1e6eb000 0x200>;
805 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
806 resets = <&rst ASPEED_RESET_DP> ,<&rst ASPEED_RESET_DP_MCU>;
807 status = "disabled";
808 };
809
810 };
811
812 };
813
814};
815
816&i2c {
817 i2cglobal: i2cg@00 {
818 compatible = "aspeed,ast2600-i2c-global";
819 reg = <0x0 0x40>;
820 resets = <&rst ASPEED_RESET_I2C>;
821#if 0
822 new-mode;
823#endif
824 };
825
826 i2c0: i2c@80 {
827 #address-cells = <1>;
828 #size-cells = <0>;
829 #interrupt-cells = <1>;
830
831 reg = <0x80 0x80 0xC00 0x20>;
832 compatible = "aspeed,ast2600-i2c-bus";
833 bus-frequency = <100000>;
834 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
835 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James8c301922022-06-23 14:40:31 +0930[diff] [blame^]836 pinctrl-names = "default";
837 pinctrl-0 = <&pinctrl_i2c1_default>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]838 status = "disabled";
839 };
840
841 i2c1: i2c@100 {
842 #address-cells = <1>;
843 #size-cells = <0>;
844 #interrupt-cells = <1>;
845
846 reg = <0x100 0x80 0xC20 0x20>;
847 compatible = "aspeed,ast2600-i2c-bus";
848 bus-frequency = <100000>;
849 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
850 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James8c301922022-06-23 14:40:31 +0930[diff] [blame^]851 pinctrl-names = "default";
852 pinctrl-0 = <&pinctrl_i2c2_default>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]853 status = "disabled";
854 };
855
856 i2c2: i2c@180 {
857 #address-cells = <1>;
858 #size-cells = <0>;
859 #interrupt-cells = <1>;
860
861 reg = <0x180 0x80 0xC40 0x20>;
862 compatible = "aspeed,ast2600-i2c-bus";
863 bus-frequency = <100000>;
864 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
865 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James8c301922022-06-23 14:40:31 +0930[diff] [blame^]866 pinctrl-names = "default";
867 pinctrl-0 = <&pinctrl_i2c3_default>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]868 };
869
870 i2c3: i2c@200 {
871 #address-cells = <1>;
872 #size-cells = <0>;
873 #interrupt-cells = <1>;
874
875 reg = <0x200 0x40 0xC60 0x20>;
876 compatible = "aspeed,ast2600-i2c-bus";
877 bus-frequency = <100000>;
878 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
879 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James8c301922022-06-23 14:40:31 +0930[diff] [blame^]880 pinctrl-names = "default";
881 pinctrl-0 = <&pinctrl_i2c4_default>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]882 };
883
884 i2c4: i2c@280 {
885 #address-cells = <1>;
886 #size-cells = <0>;
887 #interrupt-cells = <1>;
888
889 reg = <0x280 0x80 0xC80 0x20>;
890 compatible = "aspeed,ast2600-i2c-bus";
891 bus-frequency = <100000>;
892 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
893 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James8c301922022-06-23 14:40:31 +0930[diff] [blame^]894 pinctrl-names = "default";
895 pinctrl-0 = <&pinctrl_i2c5_default>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]896 };
897
898 i2c5: i2c@300 {
899 #address-cells = <1>;
900 #size-cells = <0>;
901 #interrupt-cells = <1>;
902
903 reg = <0x300 0x40 0xCA0 0x20>;
904 compatible = "aspeed,ast2600-i2c-bus";
905 bus-frequency = <100000>;
906 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
907 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James8c301922022-06-23 14:40:31 +0930[diff] [blame^]908 pinctrl-names = "default";
909 pinctrl-0 = <&pinctrl_i2c6_default>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]910 };
911
912 i2c6: i2c@380 {
913 #address-cells = <1>;
914 #size-cells = <0>;
915 #interrupt-cells = <1>;
916
917 reg = <0x380 0x80 0xCC0 0x20>;
918 compatible = "aspeed,ast2600-i2c-bus";
919 bus-frequency = <100000>;
920 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
921 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James8c301922022-06-23 14:40:31 +0930[diff] [blame^]922 pinctrl-names = "default";
923 pinctrl-0 = <&pinctrl_i2c7_default>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]924 };
925
926 i2c7: i2c@400 {
927 #address-cells = <1>;
928 #size-cells = <0>;
929 #interrupt-cells = <1>;
930
931 reg = <0x400 0x80 0xCE0 0x20>;
932 compatible = "aspeed,ast2600-i2c-bus";
933 bus-frequency = <100000>;
934 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
935 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James8c301922022-06-23 14:40:31 +0930[diff] [blame^]936 pinctrl-names = "default";
937 pinctrl-0 = <&pinctrl_i2c8_default>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]938 };
939
940 i2c8: i2c@480 {
941 #address-cells = <1>;
942 #size-cells = <0>;
943 #interrupt-cells = <1>;
944
945 reg = <0x480 0x80 0xD00 0x20>;
946 compatible = "aspeed,ast2600-i2c-bus";
947 bus-frequency = <100000>;
948 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
949 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James8c301922022-06-23 14:40:31 +0930[diff] [blame^]950 pinctrl-names = "default";
951 pinctrl-0 = <&pinctrl_i2c9_default>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]952 };
953
954 i2c9: i2c@500 {
955 #address-cells = <1>;
956 #size-cells = <0>;
957 #interrupt-cells = <1>;
958
959 reg = <0x500 0x80 0xD20 0x20>;
960 compatible = "aspeed,ast2600-i2c-bus";
961 bus-frequency = <100000>;
962 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
963 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James8c301922022-06-23 14:40:31 +0930[diff] [blame^]964 pinctrl-names = "default";
965 pinctrl-0 = <&pinctrl_i2c10_default>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]966 status = "disabled";
967 };
968
969 i2c10: i2c@580 {
970 #address-cells = <1>;
971 #size-cells = <0>;
972 #interrupt-cells = <1>;
973
974 reg = <0x580 0x80 0xD40 0x20>;
975 compatible = "aspeed,ast2600-i2c-bus";
976 bus-frequency = <100000>;
977 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
978 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James8c301922022-06-23 14:40:31 +0930[diff] [blame^]979 pinctrl-names = "default";
980 pinctrl-0 = <&pinctrl_i2c11_default>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]981 status = "disabled";
982 };
983
984 i2c11: i2c@600 {
985 #address-cells = <1>;
986 #size-cells = <0>;
987 #interrupt-cells = <1>;
988
989 reg = <0x600 0x80 0xD60 0x20>;
990 compatible = "aspeed,ast2600-i2c-bus";
991 bus-frequency = <100000>;
992 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
993 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James8c301922022-06-23 14:40:31 +0930[diff] [blame^]994 pinctrl-names = "default";
995 pinctrl-0 = <&pinctrl_i2c12_default>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]996 status = "disabled";
997 };
998
999 i2c12: i2c@680 {
1000 #address-cells = <1>;
1001 #size-cells = <0>;
1002 #interrupt-cells = <1>;
1003
1004 reg = <0x680 0x80 0xD80 0x20>;
1005 compatible = "aspeed,ast2600-i2c-bus";
1006 bus-frequency = <100000>;
1007 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1008 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James8c301922022-06-23 14:40:31 +0930[diff] [blame^]1009 pinctrl-names = "default";
1010 pinctrl-0 = <&pinctrl_i2c13_default>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]1011 status = "disabled";
1012 };
1013
1014 i2c13: i2c@700 {
1015 #address-cells = <1>;
1016 #size-cells = <0>;
1017 #interrupt-cells = <1>;
1018
1019 reg = <0x700 0x80 0xDA0 0x20>;
1020 compatible = "aspeed,ast2600-i2c-bus";
1021 bus-frequency = <100000>;
1022 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1023 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James8c301922022-06-23 14:40:31 +0930[diff] [blame^]1024 pinctrl-names = "default";
1025 pinctrl-0 = <&pinctrl_i2c14_default>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]1026 status = "disabled";
1027 };
1028
1029 i2c14: i2c@780 {
1030 #address-cells = <1>;
1031 #size-cells = <0>;
1032 #interrupt-cells = <1>;
1033
1034 reg = <0x780 0x80 0xDC0 0x20>;
1035 compatible = "aspeed,ast2600-i2c-bus";
1036 bus-frequency = <100000>;
1037 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
1038 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James8c301922022-06-23 14:40:31 +0930[diff] [blame^]1039 pinctrl-names = "default";
1040 pinctrl-0 = <&pinctrl_i2c15_default>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]1041 status = "disabled";
1042 };
1043
1044 i2c15: i2c@800 {
1045 #address-cells = <1>;
1046 #size-cells = <0>;
1047 #interrupt-cells = <1>;
1048
1049 reg = <0x800 0x80 0xDE0 0x20>;
1050 compatible = "aspeed,ast2600-i2c-bus";
1051 bus-frequency = <100000>;
1052 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
1053 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James8c301922022-06-23 14:40:31 +0930[diff] [blame^]1054 pinctrl-names = "default";
1055 pinctrl-0 = <&pinctrl_i2c16_default>;
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]1056 status = "disabled";
1057 };
1058
1059};
1060
1061&pinctrl {
1062 pinctrl_fmcquad_default: fmcquad_default {
1063 function = "FMCQUAD";
1064 groups = "FMCQUAD";
1065 };
1066
1067 pinctrl_spi1_default: spi1_default {
1068 function = "SPI1";
1069 groups = "SPI1";
1070 };
1071
1072 pinctrl_spi1abr_default: spi1abr_default {
1073 function = "SPI1ABR";
1074 groups = "SPI1ABR";
1075 };
1076
1077 pinctrl_spi1cs1_default: spi1cs1_default {
1078 function = "SPI1CS1";
1079 groups = "SPI1CS1";
1080 };
1081
1082 pinctrl_spi1wp_default: spi1wp_default {
1083 function = "SPI1WP";
1084 groups = "SPI1WP";
1085 };
1086
1087 pinctrl_spi1quad_default: spi1quad_default {
1088 function = "SPI1QUAD";
1089 groups = "SPI1QUAD";
1090 };
1091
1092 pinctrl_spi2_default: spi2_default {
1093 function = "SPI2";
1094 groups = "SPI2";
1095 };
1096
1097 pinctrl_spi2cs1_default: spi2cs1_default {
1098 function = "SPI2CS1";
1099 groups = "SPI2CS1";
1100 };
1101
1102 pinctrl_spi2cs2_default: spi2cs2_default {
1103 function = "SPI2CS2";
1104 groups = "SPI2CS2";
1105 };
1106
1107 pinctrl_spi2quad_default: spi2quad_default {
1108 function = "SPI2QUAD";
1109 groups = "SPI2QUAD";
1110 };
1111
1112 pinctrl_acpi_default: acpi_default {
1113 function = "ACPI";
1114 groups = "ACPI";
1115 };
1116
1117 pinctrl_adc0_default: adc0_default {
1118 function = "ADC0";
1119 groups = "ADC0";
1120 };
1121
1122 pinctrl_adc1_default: adc1_default {
1123 function = "ADC1";
1124 groups = "ADC1";
1125 };
1126
1127 pinctrl_adc10_default: adc10_default {
1128 function = "ADC10";
1129 groups = "ADC10";
1130 };
1131
1132 pinctrl_adc11_default: adc11_default {
1133 function = "ADC11";
1134 groups = "ADC11";
1135 };
1136
1137 pinctrl_adc12_default: adc12_default {
1138 function = "ADC12";
1139 groups = "ADC12";
1140 };
1141
1142 pinctrl_adc13_default: adc13_default {
1143 function = "ADC13";
1144 groups = "ADC13";
1145 };
1146
1147 pinctrl_adc14_default: adc14_default {
1148 function = "ADC14";
1149 groups = "ADC14";
1150 };
1151
1152 pinctrl_adc15_default: adc15_default {
1153 function = "ADC15";
1154 groups = "ADC15";
1155 };
1156
1157 pinctrl_adc2_default: adc2_default {
1158 function = "ADC2";
1159 groups = "ADC2";
1160 };
1161
1162 pinctrl_adc3_default: adc3_default {
1163 function = "ADC3";
1164 groups = "ADC3";
1165 };
1166
1167 pinctrl_adc4_default: adc4_default {
1168 function = "ADC4";
1169 groups = "ADC4";
1170 };
1171
1172 pinctrl_adc5_default: adc5_default {
1173 function = "ADC5";
1174 groups = "ADC5";
1175 };
1176
1177 pinctrl_adc6_default: adc6_default {
1178 function = "ADC6";
1179 groups = "ADC6";
1180 };
1181
1182 pinctrl_adc7_default: adc7_default {
1183 function = "ADC7";
1184 groups = "ADC7";
1185 };
1186
1187 pinctrl_adc8_default: adc8_default {
1188 function = "ADC8";
1189 groups = "ADC8";
1190 };
1191
1192 pinctrl_adc9_default: adc9_default {
1193 function = "ADC9";
1194 groups = "ADC9";
1195 };
1196
1197 pinctrl_bmcint_default: bmcint_default {
1198 function = "BMCINT";
1199 groups = "BMCINT";
1200 };
1201
1202 pinctrl_ddcclk_default: ddcclk_default {
1203 function = "DDCCLK";
1204 groups = "DDCCLK";
1205 };
1206
1207 pinctrl_ddcdat_default: ddcdat_default {
1208 function = "DDCDAT";
1209 groups = "DDCDAT";
1210 };
1211
1212 pinctrl_espi_default: espi_default {
1213 function = "ESPI";
1214 groups = "ESPI";
1215 };
1216
1217 pinctrl_fsi1_default: fsi1_default {
1218 function = "FSI1";
1219 groups = "FSI1";
1220 };
1221
1222 pinctrl_fsi2_default: fsi2_default {
1223 function = "FSI2";
1224 groups = "FSI2";
1225 };
1226
1227 pinctrl_fwspics1_default: fwspics1_default {
1228 function = "FWSPICS1";
1229 groups = "FWSPICS1";
1230 };
1231
1232 pinctrl_fwspics2_default: fwspics2_default {
1233 function = "FWSPICS2";
1234 groups = "FWSPICS2";
1235 };
1236
1237 pinctrl_gpid0_default: gpid0_default {
1238 function = "GPID0";
1239 groups = "GPID0";
1240 };
1241
1242 pinctrl_gpid2_default: gpid2_default {
1243 function = "GPID2";
1244 groups = "GPID2";
1245 };
1246
1247 pinctrl_gpid4_default: gpid4_default {
1248 function = "GPID4";
1249 groups = "GPID4";
1250 };
1251
1252 pinctrl_gpid6_default: gpid6_default {
1253 function = "GPID6";
1254 groups = "GPID6";
1255 };
1256
1257 pinctrl_gpie0_default: gpie0_default {
1258 function = "GPIE0";
1259 groups = "GPIE0";
1260 };
1261
1262 pinctrl_gpie2_default: gpie2_default {
1263 function = "GPIE2";
1264 groups = "GPIE2";
1265 };
1266
1267 pinctrl_gpie4_default: gpie4_default {
1268 function = "GPIE4";
1269 groups = "GPIE4";
1270 };
1271
1272 pinctrl_gpie6_default: gpie6_default {
1273 function = "GPIE6";
1274 groups = "GPIE6";
1275 };
1276
1277 pinctrl_i2c1_default: i2c1_default {
1278 function = "I2C1";
1279 groups = "I2C1";
1280 };
Eddie James8c301922022-06-23 14:40:31 +0930[diff] [blame^]1281
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]1282 pinctrl_i2c2_default: i2c2_default {
1283 function = "I2C2";
1284 groups = "I2C2";
1285 };
1286
1287 pinctrl_i2c3_default: i2c3_default {
1288 function = "I2C3";
1289 groups = "I2C3";
1290 };
1291
1292 pinctrl_i2c4_default: i2c4_default {
1293 function = "I2C4";
1294 groups = "I2C4";
1295 };
1296
1297 pinctrl_i2c5_default: i2c5_default {
1298 function = "I2C5";
1299 groups = "I2C5";
1300 };
1301
1302 pinctrl_i2c6_default: i2c6_default {
1303 function = "I2C6";
1304 groups = "I2C6";
1305 };
1306
1307 pinctrl_i2c7_default: i2c7_default {
1308 function = "I2C7";
1309 groups = "I2C7";
1310 };
1311
1312 pinctrl_i2c8_default: i2c8_default {
1313 function = "I2C8";
1314 groups = "I2C8";
1315 };
1316
1317 pinctrl_i2c9_default: i2c9_default {
1318 function = "I2C9";
1319 groups = "I2C9";
1320 };
1321
1322 pinctrl_i2c10_default: i2c10_default {
1323 function = "I2C10";
1324 groups = "I2C10";
1325 };
1326
1327 pinctrl_i2c11_default: i2c11_default {
1328 function = "I2C11";
1329 groups = "I2C11";
1330 };
1331
1332 pinctrl_i2c12_default: i2c12_default {
1333 function = "I2C12";
1334 groups = "I2C12";
1335 };
1336
1337 pinctrl_i2c13_default: i2c13_default {
1338 function = "I2C13";
1339 groups = "I2C13";
1340 };
1341
1342 pinctrl_i2c14_default: i2c14_default {
1343 function = "I2C14";
1344 groups = "I2C14";
1345 };
1346
1347 pinctrl_i2c15_default: i2c15_default {
1348 function = "I2C15";
1349 groups = "I2C15";
1350 };
1351
1352 pinctrl_i2c16_default: i2c16_default {
1353 function = "I2C16";
1354 groups = "I2C16";
1355 };
1356
1357 pinctrl_lad0_default: lad0_default {
1358 function = "LAD0";
1359 groups = "LAD0";
1360 };
1361
1362 pinctrl_lad1_default: lad1_default {
1363 function = "LAD1";
1364 groups = "LAD1";
1365 };
1366
1367 pinctrl_lad2_default: lad2_default {
1368 function = "LAD2";
1369 groups = "LAD2";
1370 };
1371
1372 pinctrl_lad3_default: lad3_default {
1373 function = "LAD3";
1374 groups = "LAD3";
1375 };
1376
1377 pinctrl_lclk_default: lclk_default {
1378 function = "LCLK";
1379 groups = "LCLK";
1380 };
1381
1382 pinctrl_lframe_default: lframe_default {
1383 function = "LFRAME";
1384 groups = "LFRAME";
1385 };
1386
1387 pinctrl_lpchc_default: lpchc_default {
1388 function = "LPCHC";
1389 groups = "LPCHC";
1390 };
1391
1392 pinctrl_lpcpd_default: lpcpd_default {
1393 function = "LPCPD";
1394 groups = "LPCPD";
1395 };
1396
1397 pinctrl_lpcplus_default: lpcplus_default {
1398 function = "LPCPLUS";
1399 groups = "LPCPLUS";
1400 };
1401
1402 pinctrl_lpcpme_default: lpcpme_default {
1403 function = "LPCPME";
1404 groups = "LPCPME";
1405 };
1406
1407 pinctrl_lpcrst_default: lpcrst_default {
1408 function = "LPCRST";
1409 groups = "LPCRST";
1410 };
1411
1412 pinctrl_lpcsmi_default: lpcsmi_default {
1413 function = "LPCSMI";
1414 groups = "LPCSMI";
1415 };
1416
1417 pinctrl_lsirq_default: lsirq_default {
1418 function = "LSIRQ";
1419 groups = "LSIRQ";
1420 };
1421
1422 pinctrl_mac1link_default: mac1link_default {
1423 function = "MAC1LINK";
1424 groups = "MAC1LINK";
1425 };
1426
1427 pinctrl_mac2link_default: mac2link_default {
1428 function = "MAC2LINK";
1429 groups = "MAC2LINK";
1430 };
1431
1432 pinctrl_mac3link_default: mac3link_default {
1433 function = "MAC3LINK";
1434 groups = "MAC3LINK";
1435 };
1436
1437 pinctrl_mac4link_default: mac4link_default {
1438 function = "MAC4LINK";
1439 groups = "MAC4LINK";
1440 };
1441
1442 pinctrl_mdio1_default: mdio1_default {
1443 function = "MDIO1";
1444 groups = "MDIO1";
1445 };
1446
1447 pinctrl_mdio2_default: mdio2_default {
1448 function = "MDIO2";
1449 groups = "MDIO2";
1450 };
1451
1452 pinctrl_mdio3_default: mdio3_default {
1453 function = "MDIO3";
1454 groups = "MDIO3";
1455 };
1456
1457 pinctrl_mdio4_default: mdio4_default {
1458 function = "MDIO4";
1459 groups = "MDIO4";
1460 };
1461
1462 pinctrl_rmii1_default: rmii1_default {
1463 function = "RMII1";
1464 groups = "RMII1";
1465 };
1466
1467 pinctrl_rmii2_default: rmii2_default {
1468 function = "RMII2";
1469 groups = "RMII2";
1470 };
1471
1472 pinctrl_rmii3_default: rmii3_default {
1473 function = "RMII3";
1474 groups = "RMII3";
1475 };
1476
1477 pinctrl_rmii4_default: rmii4_default {
1478 function = "RMII4";
1479 groups = "RMII4";
1480 };
1481
1482 pinctrl_rmii1rclk_default: rmii1rclk_default {
1483 function = "RMII1RCLK";
1484 groups = "RMII1RCLK";
1485 };
1486
1487 pinctrl_rmii2rclk_default: rmii2rclk_default {
1488 function = "RMII2RCLK";
1489 groups = "RMII2RCLK";
1490 };
1491
1492 pinctrl_rmii3rclk_default: rmii3rclk_default {
1493 function = "RMII3RCLK";
1494 groups = "RMII3RCLK";
1495 };
1496
1497 pinctrl_rmii4rclk_default: rmii4rclk_default {
1498 function = "RMII4RCLK";
1499 groups = "RMII4RCLK";
1500 };
1501
1502 pinctrl_ncts1_default: ncts1_default {
1503 function = "NCTS1";
1504 groups = "NCTS1";
1505 };
1506
1507 pinctrl_ncts2_default: ncts2_default {
1508 function = "NCTS2";
1509 groups = "NCTS2";
1510 };
1511
1512 pinctrl_ncts3_default: ncts3_default {
1513 function = "NCTS3";
1514 groups = "NCTS3";
1515 };
1516
1517 pinctrl_ncts4_default: ncts4_default {
1518 function = "NCTS4";
1519 groups = "NCTS4";
1520 };
1521
1522 pinctrl_ndcd1_default: ndcd1_default {
1523 function = "NDCD1";
1524 groups = "NDCD1";
1525 };
1526
1527 pinctrl_ndcd2_default: ndcd2_default {
1528 function = "NDCD2";
1529 groups = "NDCD2";
1530 };
1531
1532 pinctrl_ndcd3_default: ndcd3_default {
1533 function = "NDCD3";
1534 groups = "NDCD3";
1535 };
1536
1537 pinctrl_ndcd4_default: ndcd4_default {
1538 function = "NDCD4";
1539 groups = "NDCD4";
1540 };
1541
1542 pinctrl_ndsr1_default: ndsr1_default {
1543 function = "NDSR1";
1544 groups = "NDSR1";
1545 };
1546
1547 pinctrl_ndsr2_default: ndsr2_default {
1548 function = "NDSR2";
1549 groups = "NDSR2";
1550 };
1551
1552 pinctrl_ndsr3_default: ndsr3_default {
1553 function = "NDSR3";
1554 groups = "NDSR3";
1555 };
1556
1557 pinctrl_ndsr4_default: ndsr4_default {
1558 function = "NDSR4";
1559 groups = "NDSR4";
1560 };
1561
1562 pinctrl_ndtr1_default: ndtr1_default {
1563 function = "NDTR1";
1564 groups = "NDTR1";
1565 };
1566
1567 pinctrl_ndtr2_default: ndtr2_default {
1568 function = "NDTR2";
1569 groups = "NDTR2";
1570 };
1571
1572 pinctrl_ndtr3_default: ndtr3_default {
1573 function = "NDTR3";
1574 groups = "NDTR3";
1575 };
1576
1577 pinctrl_ndtr4_default: ndtr4_default {
1578 function = "NDTR4";
1579 groups = "NDTR4";
1580 };
1581
1582 pinctrl_nri1_default: nri1_default {
1583 function = "NRI1";
1584 groups = "NRI1";
1585 };
1586
1587 pinctrl_nri2_default: nri2_default {
1588 function = "NRI2";
1589 groups = "NRI2";
1590 };
1591
1592 pinctrl_nri3_default: nri3_default {
1593 function = "NRI3";
1594 groups = "NRI3";
1595 };
1596
1597 pinctrl_nri4_default: nri4_default {
1598 function = "NRI4";
1599 groups = "NRI4";
1600 };
1601
1602 pinctrl_nrts1_default: nrts1_default {
1603 function = "NRTS1";
1604 groups = "NRTS1";
1605 };
1606
1607 pinctrl_nrts2_default: nrts2_default {
1608 function = "NRTS2";
1609 groups = "NRTS2";
1610 };
1611
1612 pinctrl_nrts3_default: nrts3_default {
1613 function = "NRTS3";
1614 groups = "NRTS3";
1615 };
1616
1617 pinctrl_nrts4_default: nrts4_default {
1618 function = "NRTS4";
1619 groups = "NRTS4";
1620 };
1621
1622 pinctrl_oscclk_default: oscclk_default {
1623 function = "OSCCLK";
1624 groups = "OSCCLK";
1625 };
1626
1627 pinctrl_pewake_default: pewake_default {
1628 function = "PEWAKE";
1629 groups = "PEWAKE";
1630 };
1631
1632 pinctrl_pnor_default: pnor_default {
1633 function = "PNOR";
1634 groups = "PNOR";
1635 };
1636
1637 pinctrl_pwm0_default: pwm0_default {
1638 function = "PWM0";
1639 groups = "PWM0";
1640 };
1641
1642 pinctrl_pwm1_default: pwm1_default {
1643 function = "PWM1";
1644 groups = "PWM1";
1645 };
1646
1647 pinctrl_pwm2_default: pwm2_default {
1648 function = "PWM2";
1649 groups = "PWM2";
1650 };
1651
1652 pinctrl_pwm3_default: pwm3_default {
1653 function = "PWM3";
1654 groups = "PWM3";
1655 };
1656
1657 pinctrl_pwm4_default: pwm4_default {
1658 function = "PWM4";
1659 groups = "PWM4";
1660 };
1661
1662 pinctrl_pwm5_default: pwm5_default {
1663 function = "PWM5";
1664 groups = "PWM5";
1665 };
1666
1667 pinctrl_pwm6_default: pwm6_default {
1668 function = "PWM6";
1669 groups = "PWM6";
1670 };
1671
1672 pinctrl_pwm7_default: pwm7_default {
1673 function = "PWM7";
1674 groups = "PWM7";
1675 };
1676
Billy Tsai73ee1f22022-03-08 11:04:06 +0800[diff] [blame]1677 pinctrl_pwm8g0_default: pwm8g0_default {
1678 function = "PWM8G0";
1679 groups = "PWM8G0";
1680 };
1681
1682 pinctrl_pwm8g1_default: pwm8g1_default {
1683 function = "PWM8G1";
1684 groups = "PWM8G1";
1685 };
1686
1687 pinctrl_pwm9g0_default: pwm9g0_default {
1688 function = "PWM9G0";
1689 groups = "PWM9G0";
1690 };
1691
1692 pinctrl_pwm9g1_default: pwm9g1_default {
1693 function = "PWM9G1";
1694 groups = "PWM9G1";
1695 };
1696
1697 pinctrl_pwm10g0_default: pwm10g0_default {
1698 function = "PWM10G0";
1699 groups = "PWM10G0";
1700 };
1701
1702 pinctrl_pwm10g1_default: pwm10g1_default {
1703 function = "PWM10G1";
1704 groups = "PWM10G1";
1705 };
1706
1707 pinctrl_pwm11g0_default: pwm11g0_default {
1708 function = "PWM11G0";
1709 groups = "PWM11G0";
1710 };
1711
1712 pinctrl_pwm11g1_default: pwm11g1_default {
1713 function = "PWM11G1";
1714 groups = "PWM11G1";
1715 };
1716
1717 pinctrl_pwm12g0_default: pwm12g0_default {
1718 function = "PWM12G0";
1719 groups = "PWM12G0";
1720 };
1721
1722 pinctrl_pwm12g1_default: pwm12g1_default {
1723 function = "PWM12G1";
1724 groups = "PWM12G1";
1725 };
1726
1727 pinctrl_pwm13g0_default: pwm13g0_default {
1728 function = "PWM13G0";
1729 groups = "PWM13G0";
1730 };
1731
1732 pinctrl_pwm13g1_default: pwm13g1_default {
1733 function = "PWM13G1";
1734 groups = "PWM13G1";
1735 };
1736
1737 pinctrl_pwm14g0_default: pwm14g0_default {
1738 function = "PWM14G0";
1739 groups = "PWM14G0";
1740 };
1741
1742 pinctrl_pwm14g1_default: pwm14g1_default {
1743 function = "PWM14G1";
1744 groups = "PWM14G1";
1745 };
1746
1747 pinctrl_pwm15g0_default: pwm15g0_default {
1748 function = "PWM15G0";
1749 groups = "PWM15G0";
1750 };
1751
1752 pinctrl_pwm15g1_default: pwm15g1_default {
1753 function = "PWM15G1";
1754 groups = "PWM15G1";
1755 };
1756
Chia-Wei, Wangec55a1d2020-12-14 13:54:27 +0800[diff] [blame]1757 pinctrl_rgmii1_default: rgmii1_default {
1758 function = "RGMII1";
1759 groups = "RGMII1";
1760 };
1761
1762 pinctrl_rgmii2_default: rgmii2_default {
1763 function = "RGMII2";
1764 groups = "RGMII2";
1765 };
1766
1767 pinctrl_rgmii3_default: rgmii3_default {
1768 function = "RGMII3";
1769 groups = "RGMII3";
1770 };
1771
1772 pinctrl_rgmii4_default: rgmii4_default {
1773 function = "RGMII4";
1774 groups = "RGMII4";
1775 };
1776
1777 pinctrl_rmii1_default: rmii1_default {
1778 function = "RMII1";
1779 groups = "RMII1";
1780 };
1781
1782 pinctrl_rmii2_default: rmii2_default {
1783 function = "RMII2";
1784 groups = "RMII2";
1785 };
1786
1787 pinctrl_rxd1_default: rxd1_default {
1788 function = "RXD1";
1789 groups = "RXD1";
1790 };
1791
1792 pinctrl_rxd2_default: rxd2_default {
1793 function = "RXD2";
1794 groups = "RXD2";
1795 };
1796
1797 pinctrl_rxd3_default: rxd3_default {
1798 function = "RXD3";
1799 groups = "RXD3";
1800 };
1801
1802 pinctrl_rxd4_default: rxd4_default {
1803 function = "RXD4";
1804 groups = "RXD4";
1805 };
1806
1807 pinctrl_salt1_default: salt1_default {
1808 function = "SALT1";
1809 groups = "SALT1";
1810 };
1811
1812 pinctrl_salt10_default: salt10_default {
1813 function = "SALT10";
1814 groups = "SALT10";
1815 };
1816
1817 pinctrl_salt11_default: salt11_default {
1818 function = "SALT11";
1819 groups = "SALT11";
1820 };
1821
1822 pinctrl_salt12_default: salt12_default {
1823 function = "SALT12";
1824 groups = "SALT12";
1825 };
1826
1827 pinctrl_salt13_default: salt13_default {
1828 function = "SALT13";
1829 groups = "SALT13";
1830 };
1831
1832 pinctrl_salt14_default: salt14_default {
1833 function = "SALT14";
1834 groups = "SALT14";
1835 };
1836
1837 pinctrl_salt2_default: salt2_default {
1838 function = "SALT2";
1839 groups = "SALT2";
1840 };
1841
1842 pinctrl_salt3_default: salt3_default {
1843 function = "SALT3";
1844 groups = "SALT3";
1845 };
1846
1847 pinctrl_salt4_default: salt4_default {
1848 function = "SALT4";
1849 groups = "SALT4";
1850 };
1851
1852 pinctrl_salt5_default: salt5_default {
1853 function = "SALT5";
1854 groups = "SALT5";
1855 };
1856
1857 pinctrl_salt6_default: salt6_default {
1858 function = "SALT6";
1859 groups = "SALT6";
1860 };
1861
1862 pinctrl_salt7_default: salt7_default {
1863 function = "SALT7";
1864 groups = "SALT7";
1865 };
1866
1867 pinctrl_salt8_default: salt8_default {
1868 function = "SALT8";
1869 groups = "SALT8";
1870 };
1871
1872 pinctrl_salt9_default: salt9_default {
1873 function = "SALT9";
1874 groups = "SALT9";
1875 };
1876
1877 pinctrl_scl1_default: scl1_default {
1878 function = "SCL1";
1879 groups = "SCL1";
1880 };
1881
1882 pinctrl_scl2_default: scl2_default {
1883 function = "SCL2";
1884 groups = "SCL2";
1885 };
1886
1887 pinctrl_sd1_default: sd1_default {
1888 function = "SD1";
1889 groups = "SD1";
1890 };
1891
1892 pinctrl_sd2_default: sd2_default {
1893 function = "SD2";
1894 groups = "SD2";
1895 };
1896
1897 pinctrl_emmc_default: emmc_default {
1898 function = "EMMC";
1899 groups = "EMMC";
1900 };
1901
1902 pinctrl_emmcg8_default: emmcg8_default {
1903 function = "EMMCG8";
1904 groups = "EMMCG8";
1905 };
1906
1907 pinctrl_sda1_default: sda1_default {
1908 function = "SDA1";
1909 groups = "SDA1";
1910 };
1911
1912 pinctrl_sda2_default: sda2_default {
1913 function = "SDA2";
1914 groups = "SDA2";
1915 };
1916
1917 pinctrl_sgps1_default: sgps1_default {
1918 function = "SGPS1";
1919 groups = "SGPS1";
1920 };
1921
1922 pinctrl_sgps2_default: sgps2_default {
1923 function = "SGPS2";
1924 groups = "SGPS2";
1925 };
1926
1927 pinctrl_sioonctrl_default: sioonctrl_default {
1928 function = "SIOONCTRL";
1929 groups = "SIOONCTRL";
1930 };
1931
1932 pinctrl_siopbi_default: siopbi_default {
1933 function = "SIOPBI";
1934 groups = "SIOPBI";
1935 };
1936
1937 pinctrl_siopbo_default: siopbo_default {
1938 function = "SIOPBO";
1939 groups = "SIOPBO";
1940 };
1941
1942 pinctrl_siopwreq_default: siopwreq_default {
1943 function = "SIOPWREQ";
1944 groups = "SIOPWREQ";
1945 };
1946
1947 pinctrl_siopwrgd_default: siopwrgd_default {
1948 function = "SIOPWRGD";
1949 groups = "SIOPWRGD";
1950 };
1951
1952 pinctrl_sios3_default: sios3_default {
1953 function = "SIOS3";
1954 groups = "SIOS3";
1955 };
1956
1957 pinctrl_sios5_default: sios5_default {
1958 function = "SIOS5";
1959 groups = "SIOS5";
1960 };
1961
1962 pinctrl_siosci_default: siosci_default {
1963 function = "SIOSCI";
1964 groups = "SIOSCI";
1965 };
1966
1967 pinctrl_spi1_default: spi1_default {
1968 function = "SPI1";
1969 groups = "SPI1";
1970 };
1971
1972 pinctrl_spi1cs1_default: spi1cs1_default {
1973 function = "SPI1CS1";
1974 groups = "SPI1CS1";
1975 };
1976
1977 pinctrl_spi1debug_default: spi1debug_default {
1978 function = "SPI1DEBUG";
1979 groups = "SPI1DEBUG";
1980 };
1981
1982 pinctrl_spi1passthru_default: spi1passthru_default {
1983 function = "SPI1PASSTHRU";
1984 groups = "SPI1PASSTHRU";
1985 };
1986
1987 pinctrl_spi2ck_default: spi2ck_default {
1988 function = "SPI2CK";
1989 groups = "SPI2CK";
1990 };
1991
1992 pinctrl_spi2cs0_default: spi2cs0_default {
1993 function = "SPI2CS0";
1994 groups = "SPI2CS0";
1995 };
1996
1997 pinctrl_spi2cs1_default: spi2cs1_default {
1998 function = "SPI2CS1";
1999 groups = "SPI2CS1";
2000 };
2001
2002 pinctrl_spi2miso_default: spi2miso_default {
2003 function = "SPI2MISO";
2004 groups = "SPI2MISO";
2005 };
2006
2007 pinctrl_spi2mosi_default: spi2mosi_default {
2008 function = "SPI2MOSI";
2009 groups = "SPI2MOSI";
2010 };
2011
2012 pinctrl_timer3_default: timer3_default {
2013 function = "TIMER3";
2014 groups = "TIMER3";
2015 };
2016
2017 pinctrl_timer4_default: timer4_default {
2018 function = "TIMER4";
2019 groups = "TIMER4";
2020 };
2021
2022 pinctrl_timer5_default: timer5_default {
2023 function = "TIMER5";
2024 groups = "TIMER5";
2025 };
2026
2027 pinctrl_timer6_default: timer6_default {
2028 function = "TIMER6";
2029 groups = "TIMER6";
2030 };
2031
2032 pinctrl_timer7_default: timer7_default {
2033 function = "TIMER7";
2034 groups = "TIMER7";
2035 };
2036
2037 pinctrl_timer8_default: timer8_default {
2038 function = "TIMER8";
2039 groups = "TIMER8";
2040 };
2041
2042 pinctrl_txd1_default: txd1_default {
2043 function = "TXD1";
2044 groups = "TXD1";
2045 };
2046
2047 pinctrl_txd2_default: txd2_default {
2048 function = "TXD2";
2049 groups = "TXD2";
2050 };
2051
2052 pinctrl_txd3_default: txd3_default {
2053 function = "TXD3";
2054 groups = "TXD3";
2055 };
2056
2057 pinctrl_txd4_default: txd4_default {
2058 function = "TXD4";
2059 groups = "TXD4";
2060 };
2061
2062 pinctrl_uart6_default: uart6_default {
2063 function = "UART6";
2064 groups = "UART6";
2065 };
2066
2067 pinctrl_usbcki_default: usbcki_default {
2068 function = "USBCKI";
2069 groups = "USBCKI";
2070 };
2071
2072 pinctrl_usb2ah_default: usb2ah_default {
2073 function = "USB2AH";
2074 groups = "USB2AH";
2075 };
2076
2077 pinctrl_usb11bhid_default: usb11bhid_default {
2078 function = "USB11BHID";
2079 groups = "USB11BHID";
2080 };
2081
2082 pinctrl_usb2bh_default: usb2bh_default {
2083 function = "USB2BH";
2084 groups = "USB2BH";
2085 };
2086
2087 pinctrl_vgabiosrom_default: vgabiosrom_default {
2088 function = "VGABIOSROM";
2089 groups = "VGABIOSROM";
2090 };
2091
2092 pinctrl_vgahs_default: vgahs_default {
2093 function = "VGAHS";
2094 groups = "VGAHS";
2095 };
2096
2097 pinctrl_vgavs_default: vgavs_default {
2098 function = "VGAVS";
2099 groups = "VGAVS";
2100 };
2101
2102 pinctrl_vpi24_default: vpi24_default {
2103 function = "VPI24";
2104 groups = "VPI24";
2105 };
2106
2107 pinctrl_vpo_default: vpo_default {
2108 function = "VPO";
2109 groups = "VPO";
2110 };
2111
2112 pinctrl_wdtrst1_default: wdtrst1_default {
2113 function = "WDTRST1";
2114 groups = "WDTRST1";
2115 };
2116
2117 pinctrl_wdtrst2_default: wdtrst2_default {
2118 function = "WDTRST2";
2119 groups = "WDTRST2";
2120 };
2121
2122 pinctrl_pcie0rc_default: pcie0rc_default {
2123 function = "PCIE0RC";
2124 groups = "PCIE0RC";
2125 };
2126
2127 pinctrl_pcie1rc_default: pcie1rc_default {
2128 function = "PCIE1RC";
2129 groups = "PCIE1RC";
2130 };
2131};