Vladimir Barinov | 2187113 | 2015-07-20 20:49:59 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Stout board CPLD definition |
| 3 | * |
| 4 | * Copyright (C) 2015 Renesas Electronics Europe GmbH |
| 5 | * Copyright (C) 2015 Renesas Electronics Corporation |
| 6 | * Copyright (C) 2015 Cogent Embedded, Inc. |
| 7 | * |
| 8 | * SPDX-License-Identifier: GPL-2.0 |
| 9 | */ |
| 10 | |
| 11 | #ifndef _CPLD_H_ |
| 12 | #define _CPLD_H_ |
| 13 | |
| 14 | /* power-up behaviour */ |
| 15 | #define MODE_MSK_FREE_RUN 0x00000001 |
| 16 | #define MODE_VAL_FREE_RUN 0x00000000 |
| 17 | #define MODE_MSK_STEP_UP 0x00000001 |
| 18 | #define MODE_VAL_STEP_UP 0x00000000 |
| 19 | |
| 20 | /* boot source */ |
| 21 | #define MODE_MSK_BOOT_SQPI_16KB_FAST 0x0000000E |
| 22 | #define MODE_VAL_BOOT_SQPI_16KB_FAST 0x00000004 |
| 23 | #define MODE_MSK_BOOT_SQPI_16KB_SLOW 0x0000000E |
| 24 | #define MODE_VAL_BOOT_SQPI_16KB_SLOW 0x00000008 |
| 25 | #define MODE_MSK_BOOT_SQPI_4KB_SLOW 0x0000000E |
| 26 | #define MODE_VAL_BOOT_SQPI_4KB_SLOW 0x0000000C |
| 27 | |
| 28 | /* booting CPU */ |
| 29 | #define MODE_MSK_BOOT_CA15 0x000000C0 |
| 30 | #define MODE_VAL_BOOT_CA15 0x00000000 |
| 31 | #define MODE_MSK_BOOT_CA7 0x000000C0 |
| 32 | #define MODE_VAL_BOOT_CA7 0x00000040 |
| 33 | #define MODE_MSK_BOOT_SH4 0x000000C0 |
| 34 | #define MODE_VAL_BOOT_SH4 0x000000C0 |
| 35 | |
| 36 | /* JTAG connection */ |
| 37 | #define MODE_MSK_JTAG_CORESIGHT 0xC0301C00 |
| 38 | #define MODE_VAL_JTAG_CORESIGHT 0x00200000 |
| 39 | #define MODE_MSK_JTAG_SH4 0xC0301C00 |
| 40 | #define MODE_VAL_JTAG_SH4 0x00300000 |
| 41 | |
| 42 | /* DDR3 (PLL) speed */ |
| 43 | #define MODE_MSK_DDR3_1600 0x00080000 |
| 44 | #define MODE_VAL_DDR3_1600 0x00000000 |
| 45 | #define MODE_MSK_DDR3_1333 0x00080000 |
| 46 | #define MODE_VAL_DDR3_1333 0x00080000 |
| 47 | |
| 48 | /* ComboPhy0 mode */ |
| 49 | #define MODE_MSK_PHY0_SATA0 0x01000000 |
| 50 | #define MODE_VAL_PHY0_SATA0 0x00000000 |
| 51 | #define MODE_MSK_PHY0_PCIE 0x01000000 |
| 52 | #define MODE_VAL_PHY0_PCIE 0x01000000 |
| 53 | |
| 54 | /* ComboPhy1 mode */ |
| 55 | #define MODE_MSK_PHY1_SATA1 0x00800000 |
| 56 | #define MODE_VAL_PHY1_SATA1 0x00000000 |
| 57 | #define MODE_MSK_PHY1_USB3 0x00800000 |
| 58 | #define MODE_VAL_PHY1_USB3 0x00800000 |
| 59 | |
| 60 | /* |
| 61 | * Illegal multiplexer combinations. |
| 62 | * MUX Conflicts |
| 63 | * name with any one of |
| 64 | * VIN0_BT656 VIN0_full, SD2 |
| 65 | * VIN0_full VIN0_BT656, SD2, AVB, VIN2_(all) |
| 66 | * VIN1_BT656 VIN1_(others), SD0 |
| 67 | * VIN1_10bit VIN1_(others), SD0, VIN3_with*, I2C1 |
| 68 | * VIN1_12bit VIN1_(others), SD0, VIN3_with*, I2C1, SCIFA0_(all) |
| 69 | * VIN2_BT656 VIN0_full, VIN2_(others), AVB, |
| 70 | * VIN2_withSYNC VIN0_full, VIN2_(others), AVB, I2C1, SCIFA0_(all), |
| 71 | * VIN3_with* |
| 72 | * VIN2_withFIELD VIN0_full, VIN2_(others), AVB, SQPI_(all) |
| 73 | * VIN2_withSYNCandFIELD VIN0_full, VIN2_(others), AVB, SQPI_(all), I2C1, |
| 74 | * SCIFA0_(all), VIN3_with* |
| 75 | * VIN3_BT656 VIN3_(others), IRQ3 |
| 76 | * VIN3_withFIELD VIN3_(others), IRQ3, VIN1_12bit, VIN2_withSYNC, |
| 77 | * VIN2_withSYNCandFIELD, VIN1_10bit |
| 78 | * VIN3_withSYNCandFIELD VIN3_(others), IRQ3, VIN1_12bit, VIN2_withSYNC, |
| 79 | * VIN2_withSYNCandFIELD, VIN1_10bit, I2C1 |
| 80 | * AVB VIN0_full, VIN2_(all) |
| 81 | * QSPI_ONBOARD VIN2_withFIELD, VIN2_withSYNCandFIELD, QSPI_COMEXPRESS |
| 82 | * QSPI_COMEXPRESS VIN2_withFIELD, VIN2_withSYNCandFIELD, QSPI_ONBOARD |
| 83 | * I2C1 VIN1_12bit, VIN2_withSYNC, VIN2_withSYNCandFIELD, |
| 84 | * VIN3_withSYNCandFIELD |
| 85 | * IRQ3 VIN3_(all) |
| 86 | * SCIFA0_USB VIN1_12bit, VIN2_withSYNC, VIN2_withSYNCandFIELD, |
| 87 | * SCIFA0_COMEXPRESS |
| 88 | * SCIFA0_COMEXPRESS VIN1_12bit, VIN2_withSYNC, VIN2_withSYNCandFIELD, |
| 89 | * SCIFA0_USB |
| 90 | * SCIFA2 PWM210 |
| 91 | * ETH_ONBOARD ETH_COMEXPRESS |
| 92 | * ETH_COMEXPRESS ETH_ONBOARD |
| 93 | * SD0 VIN1_(all) |
| 94 | * SD2 VIN0_(all) |
| 95 | * PWM210 SCIFA2 |
| 96 | */ |
| 97 | |
| 98 | /* connected to COM Express connector and CN6 for camera, BT656 only */ |
| 99 | #define MUX_MSK_VIN0_BT656 0x00001001 |
| 100 | #define MUX_VAL_VIN0_BT656 0x00000000 |
| 101 | /* connected to COM Express connector and CN6 for camera, all modes */ |
| 102 | #define MUX_MSK_VIN0_full 0x00001007 |
| 103 | #define MUX_VAL_VIN0_full 0x00000002 |
| 104 | /* connected to COM Express connector, BT656 only */ |
| 105 | #define MUX_MSK_VIN1_BT656 0x00000801 |
| 106 | #define MUX_VAL_VIN1_BT656 0x00000800 |
| 107 | /* connected to COM Express connector, all 10-bit modes */ |
| 108 | #define MUX_MSK_VIN1_10bit 0x00000821 |
| 109 | #define MUX_VAL_VIN1_10bit 0x00000800 |
| 110 | /* connected to COM Express connector, all 12-bit modes */ |
| 111 | #define MUX_MSK_VIN1_12bit 0x000008A1 |
| 112 | #define MUX_VAL_VIN1_12bit 0x00000880 |
| 113 | /* connected to COM Express connector, BT656 only */ |
| 114 | #define MUX_MSK_VIN2_BT656 0x00000007 |
| 115 | #define MUX_VAL_VIN2_BT656 0x00000006 |
| 116 | /* connected to COM Express connector, modes with sync signals */ |
| 117 | #define MUX_MSK_VIN2_withSYNC 0x000000A7 |
| 118 | #define MUX_VAL_VIN2_withSYNC 0x00000086 |
| 119 | /* connected to COM Express connector, modes with field, clken signals */ |
| 120 | #define MUX_MSK_VIN2_withFIELD 0x0000000F |
| 121 | #define MUX_VAL_VIN2_withFIELD 0x0000000E |
| 122 | /* connected to COM Express connector, modes with sync, field, clken signals */ |
| 123 | #define MUX_MSK_VIN2_withSYNCandFIELD 0x000000AF |
| 124 | #define MUX_VAL_VIN2_withSYNCandFIELD 0x0000008E |
| 125 | /* connected to COM Express connector, BT656 only */ |
| 126 | #define MUX_MSK_VIN3_BT656 0x00000101 |
| 127 | #define MUX_VAL_VIN3_BT656 0x00000100 |
| 128 | /* connected to COM Express connector, modes with field, clken signals */ |
| 129 | #define MUX_MSK_VIN3_withFIELD 0x00000121 |
| 130 | #define MUX_VAL_VIN3_withFIELD 0x00000120 |
| 131 | /* connected to COM Express connector, modes with sync, field, clken signals */ |
| 132 | #define MUX_MSK_VIN3_withSYNCandFIELD 0x00000161 |
| 133 | #define MUX_VAL_VIN3_withSYNCandFIELD 0x00000120 |
| 134 | /* connected to COM Express connector (RGMII) */ |
| 135 | #define MUX_MSK_AVB 0x00000003 |
| 136 | #define MUX_VAL_AVB 0x00000000 |
| 137 | /* connected to on-board QSPI flash */ |
| 138 | #define MUX_MSK_QSPI_ONBOARD 0x00000019 |
| 139 | #define MUX_VAL_QSPI_ONBOARD 0x00000000 |
| 140 | /* connected to COM Express connector */ |
| 141 | #define MUX_MSK_QSPI_COMEXPRESS 0x00000019 |
| 142 | #define MUX_VAL_QSPI_COMEXPRESS 0x00000010 |
| 143 | /* connected to COM Express connector and PMIC */ |
| 144 | #define MUX_MSK_I2C1 0x00000061 |
| 145 | #define MUX_VAL_I2C1 0x00000060 |
| 146 | /* connected to HDMI driver */ |
| 147 | #define MUX_MSK_IRQ3 0x00000101 |
| 148 | #define MUX_VAL_IRQ3 0x00000000 |
| 149 | /* connected to USB/FTDI */ |
| 150 | #define MUX_MSK_SCIFA0_USB 0x00004081 |
| 151 | #define MUX_VAL_SCIFA0_USB 0x00004000 |
| 152 | /* connected to COM Express connector */ |
| 153 | #define MUX_MSK_SCIFA0_COMEXPRESS 0x00004081 |
| 154 | #define MUX_VAL_SCIFA0_COMEXPRESS 0x00000000 |
| 155 | /* connected to COM Express connector */ |
| 156 | #define MUX_MSK_SCIFA2 0x00002001 |
| 157 | #define MUX_VAL_SCIFA2 0x00000000 |
| 158 | /* connected to on-board 10/100 Phy */ |
| 159 | #define MUX_MSK_ETH_ONBOARD 0x00000600 |
| 160 | #define MUX_VAL_ETH_ONBOARD 0x00000000 |
| 161 | /* connected to COM Express connector (RMII) */ |
| 162 | #define MUX_MSK_ETH_COMEXPRESS 0x00000600 |
| 163 | #define MUX_VAL_ETH_COMEXPRESS 0x00000400 |
| 164 | /* connected to on-board MicroSD slot */ |
| 165 | #define MUX_MSK_SD0 0x00000801 |
| 166 | #define MUX_VAL_SD0 0x00000000 |
| 167 | /* connected to COM Express connector */ |
| 168 | #define MUX_MSK_SD2 0x00001001 |
| 169 | #define MUX_VAL_SD2 0x00001000 |
| 170 | /* connected to COM Express connector */ |
| 171 | #define MUX_MSK_PWM210 0x00002001 |
| 172 | #define MUX_VAL_PWM210 0x00002000 |
| 173 | |
| 174 | #define HDMI_MSK 0x07 |
| 175 | #define HDMI_OFF 0x00 |
| 176 | #define HDMI_ONBOARD 0x07 |
| 177 | #define HDMI_COMEXPRESS 0x05 |
| 178 | #define HDMI_ONBOARD_NODDC 0x03 |
| 179 | #define HDMI_COMEXPRESS_NODDC 0x01 |
| 180 | |
| 181 | void cpld_init(void); |
| 182 | |
| 183 | #endif /* _CPLD_H_ */ |