blob: 7941631b510e4ebe38a1a0dd9178c389233f1b45 [file] [log] [blame]
Markus Klotzbuecher090eb732006-07-12 15:26:01 +02001/*
2 * (C) Copyright 2000-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2006
6 * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27/*
28 * board/config.h - configuration options, board specific
29 */
30
31#ifndef __CONFIG_H
32#define __CONFIG_H
33
34/*
35 * High Level Configuration Options
36 * (easy to change)
37 */
38
39#define CONFIG_MPC885 1 /* This is a MPC885 CPU */
40#define CONFIG_TQM885D 1 /* ...on a TQM88D module */
41
Wolfgang Denk2ae18242010-10-06 09:05:45 +020042#define CONFIG_SYS_TEXT_BASE 0x40000000
43
Markus Klotzbuecher090eb732006-07-12 15:26:01 +020044#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020045#define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
46#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
Jens Gehrlein22d1a562007-09-26 17:55:54 +020047#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 66 MHz - CPU default clock */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +020048 /* (it will be used if there is no */
49 /* 'cpuclk' variable with valid value) */
50
Markus Klotzbuecher090eb732006-07-12 15:26:01 +020051#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
Wolfgang Denk3cb7a482009-07-28 22:13:52 +020052#define CONFIG_SYS_SMC_RXBUFLEN 128
53#define CONFIG_SYS_MAXIDLE 10
Markus Klotzbuecher090eb732006-07-12 15:26:01 +020054#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
55
56#define CONFIG_BOOTCOUNT_LIMIT
57
58#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
59
60#define CONFIG_BOARD_TYPES 1 /* support board types */
61
62#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010063 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +020064 "echo"
65
66#undef CONFIG_BOOTARGS
67
68#define CONFIG_EXTRA_ENV_SETTINGS \
69 "netdev=eth0\0" \
70 "nfsargs=setenv bootargs root=/dev/nfs rw " \
71 "nfsroot=${serverip}:${rootpath}\0" \
72 "ramargs=setenv bootargs root=/dev/ram rw\0" \
73 "addip=setenv bootargs ${bootargs} " \
74 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
75 ":${hostname}:${netdev}:off panic=1\0" \
76 "flash_nfs=run nfsargs addip;" \
77 "bootm ${kernel_addr}\0" \
78 "flash_self=run ramargs addip;" \
79 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
80 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
81 "rootpath=/opt/eldk/ppc_8xx\0" \
Martin Krause11d9eec2007-09-26 17:55:56 +020082 "bootfile=/tftpboot/TQM885D/uImage\0" \
83 "fdt_addr=400C0000\0" \
84 "kernel_addr=40100000\0" \
85 "ramdisk_addr=40280000\0" \
86 "load=tftp 200000 ${u-boot}\0" \
87 "update=protect off 40000000 +${filesize};" \
88 "erase 40000000 +${filesize};" \
89 "cp.b 200000 40000000 ${filesize};" \
90 "protect on 40000000 +${filesize}\0" \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +020091 ""
92#define CONFIG_BOOTCOMMAND "run flash_self"
93
94#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +020096
97#undef CONFIG_WATCHDOG /* watchdog disabled */
98
99#define CONFIG_STATUS_LED 1 /* Status LED enabled */
100
101#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
102
103/* enable I2C and select the hardware/software driver */
104#undef CONFIG_HARD_I2C /* I2C with hardware support */
105#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
106
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */
108#define CONFIG_SYS_I2C_SLAVE 0xFE
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200109
110#ifdef CONFIG_SOFT_I2C
111/*
112 * Software (bit-bang) I2C driver configuration
113 */
114#define PB_SCL 0x00000020 /* PB 26 */
115#define PB_SDA 0x00000010 /* PB 27 */
116
117#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
118#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
119#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
120#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
121#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
122 else immr->im_cpm.cp_pbdat &= ~PB_SDA
123#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
124 else immr->im_cpm.cp_pbdat &= ~PB_SCL
125#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
126#endif /* CONFIG_SOFT_I2C */
127
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */
129#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
130#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
131#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200132
133# define CONFIG_RTC_DS1337 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134# define CONFIG_SYS_I2C_RTC_ADDR 0x68
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200135
Jon Loeliger37d4bb72007-07-09 21:38:02 -0500136/*
137 * BOOTP options
138 */
139#define CONFIG_BOOTP_SUBNETMASK
140#define CONFIG_BOOTP_GATEWAY
141#define CONFIG_BOOTP_HOSTNAME
142#define CONFIG_BOOTP_BOOTPATH
143#define CONFIG_BOOTP_BOOTFILESIZE
144
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200145
146#define CONFIG_MAC_PARTITION
147#define CONFIG_DOS_PARTITION
148
Martin Krause11d9eec2007-09-26 17:55:56 +0200149#undef CONFIG_RTC_MPC8xx /* MPC885 does not support RTC */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200150
151#define CONFIG_TIMESTAMP /* but print image timestmps */
152
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200153
Jon Loeliger26946902007-07-04 22:30:50 -0500154/*
155 * Command line configuration.
156 */
157#include <config_cmd_default.h>
158
159#define CONFIG_CMD_ASKENV
160#define CONFIG_CMD_DATE
161#define CONFIG_CMD_DHCP
162#define CONFIG_CMD_EEPROM
Wolfgang Denk9a63b7f2009-02-21 21:51:21 +0100163#define CONFIG_CMD_EXT2
Jon Loeliger26946902007-07-04 22:30:50 -0500164#define CONFIG_CMD_I2C
165#define CONFIG_CMD_IDE
166#define CONFIG_CMD_MII
167#define CONFIG_CMD_NFS
168#define CONFIG_CMD_PING
169
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200170
171/*
172 * Miscellaneous configurable options
173 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_LONGHELP /* undef to save memory */
175#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200176
Wolfgang Denk2751a952006-10-28 02:29:14 +0200177#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200179
Jon Loeliger26946902007-07-04 22:30:50 -0500180#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200182#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200184#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
186#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
187#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200188
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
190#define CONFIG_SYS_MEMTEST_END 0x0300000 /* 1 ... 3 MB in DRAM */
191#define CONFIG_SYS_ALT_MEMTEST /* alternate, more extensive
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200192 memory test.*/
193
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200195
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200197
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200198/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -0500199 * Enable loopw command.
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200200 */
201#define CONFIG_LOOPW
202
203/*
204 * Low Level Configuration Settings
205 * (address mappings, register initial values, etc.)
206 * You should know what you are doing if you make changes here.
207 */
208/*-----------------------------------------------------------------------
209 * Internal Memory Mapped Register
210 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_IMMR 0xFFF00000
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200212
213/*-----------------------------------------------------------------------
214 * Definitions for initial stack pointer and data area (in DPRAM)
215 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200217#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200218#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200220
221/*-----------------------------------------------------------------------
222 * Start addresses for the final memory configuration
223 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200225 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_SDRAM_BASE 0x00000000
227#define CONFIG_SYS_FLASH_BASE 0x40000000
228#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
229#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
230#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200231
232/*
233 * For booting Linux, the board info and command line data
234 * have to be in the first 8 MB of memory, since this is
235 * the maximum mapped by the Linux kernel during initialization.
236 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200238
239/*-----------------------------------------------------------------------
240 * FLASH organization
241 */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200242
Martin Krausee318d9e2007-09-27 11:10:08 +0200243/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200245#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
247#define CONFIG_SYS_FLASH_EMPTY_INFO
248#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
249#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
250#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200251
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200252#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200253#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
254#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */
255#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200256
257/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200258#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
259#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200260
261/*-----------------------------------------------------------------------
262 * Hardware Information Block
263 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
265#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
266#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200267
268/*-----------------------------------------------------------------------
269 * Cache Configuration
270 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger26946902007-07-04 22:30:50 -0500272#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200274#endif
275
276/*-----------------------------------------------------------------------
277 * SYPCR - System Protection Control 11-9
278 * SYPCR can only be written once after reset!
279 *-----------------------------------------------------------------------
280 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
281 */
282#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200284 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
285#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200287#endif
288
289/*-----------------------------------------------------------------------
290 * SIUMCR - SIU Module Configuration 11-6
291 *-----------------------------------------------------------------------
292 * PCMCIA config., multi-function pin tri-state
293 */
294#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200296#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200298#endif /* CONFIG_CAN_DRIVER */
299
300/*-----------------------------------------------------------------------
301 * TBSCR - Time Base Status and Control 11-26
302 *-----------------------------------------------------------------------
303 * Clear Reference Interrupt Status, Timebase freezing enabled
304 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200306
307/*-----------------------------------------------------------------------
308 * PISCR - Periodic Interrupt Status and Control 11-31
309 *-----------------------------------------------------------------------
310 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
311 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200313
314/*-----------------------------------------------------------------------
315 * SCCR - System Clock and reset Control Register 15-27
316 *-----------------------------------------------------------------------
317 * Set clock output, timebase and RTC source and divider,
318 * power management and some other internal clocks
319 */
320#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200322 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
323 SCCR_DFALCD00)
324
325/*-----------------------------------------------------------------------
326 * PCMCIA stuff
327 *-----------------------------------------------------------------------
328 *
329 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
331#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
332#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
333#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
334#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
335#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
336#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
337#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200338
339/*-----------------------------------------------------------------------
340 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
341 *-----------------------------------------------------------------------
342 */
343
Pavel Herrmann8d1165e11a2012-10-09 07:01:56 +0000344#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200345#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
346
347#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
348#undef CONFIG_IDE_LED /* LED for ide not supported */
349#undef CONFIG_IDE_RESET /* reset for ide not supported */
350
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
352#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200353
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200355
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200356#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200357
358/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200359#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200360
361/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200363
364/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200365#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200366
367/*-----------------------------------------------------------------------
368 *
369 *-----------------------------------------------------------------------
370 *
371 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200372#define CONFIG_SYS_DER 0
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200373
374/*
375 * Init Memory Controller:
376 *
377 * BR0/1 and OR0/1 (FLASH)
378 */
379
380#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
381#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
382
383/* used to re-map FLASH both when starting from SRAM or FLASH:
384 * restrict access enough to keep SRAM working (if any)
385 * but not too much to meddle with FLASH accesses
386 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200387#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
388#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200389
390/*
391 * FLASH timing: Default value of OR0 after reset
392 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200393#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200394 OR_SCY_6_CLK | OR_TRLX)
395
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200396#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
397#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
398#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200399
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200400#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
401#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
402#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200403
404/*
405 * BR2/3 and OR2/3 (SDRAM)
406 *
407 */
408#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
409#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
410#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */
411
412/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200413#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200414
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200415#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
416#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200417
418#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200419#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
420#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200421#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200422#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
423#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
424#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
425#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200426 BR_PS_8 | BR_MS_UPMB | BR_V )
427#endif /* CONFIG_CAN_DRIVER */
428
429/*
430 * 4096 Rows from SDRAM example configuration
431 * 1000 factor s -> ms
432 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
433 * 4 Number of refresh cycles per period
434 * 64 Refresh cycle in ms per number of rows
435 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200436#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200437
438/*
Jens Gehrlein492c7042007-09-27 14:54:46 +0200439 * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
440 *
441 * CPUclock(MHz) * 31.2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200442 * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0
Jens Gehrlein492c7042007-09-27 14:54:46 +0200443 * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
444 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200445 * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us
446 * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us
447 * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us
448 * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us
Jens Gehrlein492c7042007-09-27 14:54:46 +0200449 *
450 * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
451 * be met also in the default configuration, i.e. if environment variable
452 * 'cpuclk' is not set.
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200453 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200454#define CONFIG_SYS_MAMR_PTA 128
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200455
456/*
Jens Gehrlein492c7042007-09-27 14:54:46 +0200457 * Memory Periodic Timer Prescaler Register (MPTPR) values.
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200458 */
Jens Gehrlein492c7042007-09-27 14:54:46 +0200459/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200460#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16
Jens Gehrlein492c7042007-09-27 14:54:46 +0200461/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200462#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200463
464/*
465 * MAMR settings for SDRAM
466 */
467
468/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200469#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200470 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
471 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
472/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200473#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200474 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
475 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
476/* 10 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200477#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200478 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \
479 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
480
481/*
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200482 * Network configuration
483 */
484#define CONFIG_SCC2_ENET /* enable ethernet on SCC2 */
485#define CONFIG_FEC_ENET /* enable ethernet on FEC */
486#define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */
487#define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */
488
Jon Loeliger26946902007-07-04 22:30:50 -0500489#if defined(CONFIG_CMD_MII)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200490#define CONFIG_SYS_DISCOVER_PHY
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -0500491#define CONFIG_MII_INIT 1
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200492#endif
493
494#define CONFIG_NET_RETRY_COUNT 1 /* reduce max. timeout before
495 switching to another netwok (if the
496 tried network is unreachable) */
497
Heiko Schocher48690d82010-07-20 17:45:02 +0200498#define CONFIG_ETHPRIME "SCC"
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200499
Heiko Schocher7026ead2010-02-09 15:50:27 +0100500/* pass open firmware flat tree */
501#define CONFIG_OF_LIBFDT 1
502#define CONFIG_OF_BOARD_SETUP 1
503#define CONFIG_HWCONFIG 1
504
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200505#endif /* __CONFIG_H */