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wdenk56523f12004-07-11 17:40:54 +00001/*
2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2004
6 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28
29flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
30
31/*
32 * CPU to flash interface is 32-bit, so make declaration accordingly
33 */
34typedef unsigned long FLASH_PORT_WIDTH;
35typedef volatile unsigned long FLASH_PORT_WIDTHV;
36
37#define FPW FLASH_PORT_WIDTH
38#define FPWV FLASH_PORT_WIDTHV
39
40#define FLASH_CYCLE1 0x0555
41#define FLASH_CYCLE2 0x02aa
42
43/*-----------------------------------------------------------------------
44 * Functions
45 */
46static ulong flash_get_size(FPWV *addr, flash_info_t *info);
47static void flash_reset(flash_info_t *info);
48static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
49static flash_info_t *flash_get_info(ulong base);
50
51/*-----------------------------------------------------------------------
52 * flash_init()
53 *
54 * sets up flash_info and returns size of FLASH (bytes)
55 */
56unsigned long flash_init (void)
57{
58 unsigned long size = 0;
59 extern void flash_preinit(void);
60 ulong flashbase = CFG_FLASH_BASE;
61
62 flash_preinit();
63
64 /* Init: no FLASHes known */
65 memset(&flash_info[0], 0, sizeof(flash_info_t));
66
67 flash_info[0].size =
68 flash_get_size((FPW *)flashbase, &flash_info[0]);
69
70 size = flash_info[0].size;
71
72#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
73 /* monitor protection ON by default */
74 flash_protect(FLAG_PROTECT_SET,
75 CFG_MONITOR_BASE,
76 CFG_MONITOR_BASE+monitor_flash_len-1,
77 flash_get_info(CFG_MONITOR_BASE));
78#endif
79
80#ifdef CFG_ENV_IS_IN_FLASH
81 /* ENV protection ON by default */
82 flash_protect(FLAG_PROTECT_SET,
83 CFG_ENV_ADDR,
84 CFG_ENV_ADDR+CFG_ENV_SIZE-1,
85 flash_get_info(CFG_ENV_ADDR));
86#endif
87
88 return size ? size : 1;
89}
90
91/*-----------------------------------------------------------------------
92 */
93static void flash_reset(flash_info_t *info)
94{
95 FPWV *base = (FPWV *)(info->start[0]);
96
97 /* Put FLASH back in read mode */
98 if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
99 *base = (FPW)0x00FF00FF; /* Intel Read Mode */
100 else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
101 *base = (FPW)0x00F000F0; /* AMD Read Mode */
102}
103
104/*-----------------------------------------------------------------------
105 */
106
107static flash_info_t *flash_get_info(ulong base)
108{
109 int i;
110 flash_info_t * info;
111
112 for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
113 info = & flash_info[i];
114 if (info->size && info->start[0] <= base &&
115 base <= info->start[0] + info->size - 1)
116 break;
117 }
118
119 return i == CFG_MAX_FLASH_BANKS ? 0 : info;
120}
121
122/*-----------------------------------------------------------------------
123 */
124
125void flash_print_info (flash_info_t *info)
126{
127 int i;
128
129 if (info->flash_id == FLASH_UNKNOWN) {
130 printf ("missing or unknown FLASH type\n");
131 return;
132 }
133
134 switch (info->flash_id & FLASH_VENDMASK) {
135 case FLASH_MAN_AMD: printf ("AMD "); break;
136 case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
137 case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
138 case FLASH_MAN_SST: printf ("SST "); break;
139 case FLASH_MAN_STM: printf ("STM "); break;
140 case FLASH_MAN_INTEL: printf ("INTEL "); break;
141 default: printf ("Unknown Vendor "); break;
142 }
143
144 switch (info->flash_id & FLASH_TYPEMASK) {
145 case FLASH_AMLV128U:
146 printf ("AM29LV128ML (128Mbit, uniform sector size)\n");
147 break;
148 case FLASH_AM160B:
149 printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
150 break;
151 default:
152 printf ("Unknown Chip Type\n");
153 break;
154 }
155
156 printf (" Size: %ld MB in %d Sectors\n",
157 info->size >> 20,
158 info->sector_count);
159
160 printf (" Sector Start Addresses:");
161
162 for (i=0; i<info->sector_count; ++i) {
163 if ((i % 5) == 0) {
164 printf ("\n ");
165 }
166 printf (" %08lX%s",
167 info->start[i],
168 info->protect[i] ? " (RO)" : " ");
169 }
170 printf ("\n");
171 return;
172}
173
174/*-----------------------------------------------------------------------
175 */
176
177/*
178 * The following code cannot be run from FLASH!
179 */
180
181ulong flash_get_size (FPWV *addr, flash_info_t *info)
182{
183 int i;
184 ulong base = (ulong)addr;
185
186 /* Write auto select command: read Manufacturer ID */
187 /* Write auto select command sequence and test FLASH answer */
188 addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */
189 addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */
190 addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */
191
192 /* The manufacturer codes are only 1 byte, so just use 1 byte.
193 * This works for any bus width and any FLASH device width.
194 */
195 udelay(100);
196 switch (addr[0] & 0xff) {
197
198 case (uchar)AMD_MANUFACT:
199 debug ("Manufacturer: AMD (Spansion)\n");
200 info->flash_id = FLASH_MAN_AMD;
201 break;
202
203 case (uchar)INTEL_MANUFACT:
204 debug ("Manufacturer: Intel (not supported yet)\n");
205 info->flash_id = FLASH_MAN_INTEL;
206 break;
207
208 default:
209 info->flash_id = FLASH_UNKNOWN;
210 info->sector_count = 0;
211 info->size = 0;
212 break;
213 }
214
215 /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
216 if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[1]) {
217
218 case (FPW)AMD_ID_LV160B:
219 debug ("Chip: AM29LV160MB\n");
220 info->flash_id += FLASH_AM160B;
221 info->sector_count = 35;
222 info->size = 0x00400000;
223 /*
224 * The first 4 sectors are 16 kB, 8 kB, 8 kB and 32 kB, all
225 * the other ones are 64 kB
226 */
227 info->start[0] = base + 0x00000000;
228 info->start[1] = base + 0x00008000;
229 info->start[2] = base + 0x0000C000;
230 info->start[3] = base + 0x00010000;
231 for( i = 4; i < info->sector_count; i++ )
232 info->start[i] =
233 base + (i * 2 * (64 << 10)) - 0x00060000;
234 break; /* => 4 MB */
235
236 case AMD_ID_MIRROR:
237 debug ("Mirror Bit flash: addr[14] = %08lX addr[15] = %08lX\n",
238 addr[14], addr[15]);
239
240 switch(addr[14]) {
241 case AMD_ID_LV128U_2:
242 if (addr[15] != AMD_ID_LV128U_3) {
243 debug ("Chip: AM29LVxxxM -> unknown\n");
244 info->flash_id = FLASH_UNKNOWN;
245 info->sector_count = 0;
246 info->size = 0;
247 } else {
248 debug ("Chip: AM29LV128M\n");
249 info->flash_id += FLASH_AMLV128U;
250 info->sector_count = 256;
251 info->size = 0x02000000;
252 for (i = 0; i < info->sector_count; i++) {
253 info->start[i] = base;
254 base += 0x20000;
255 }
256 }
257 break; /* => 32 MB */
258 default:
259 debug ("Chip: *** unknown ***\n");
260 info->flash_id = FLASH_UNKNOWN;
261 info->sector_count = 0;
262 info->size = 0;
263 break;
264 }
265 break;
266
267 default:
268 info->flash_id = FLASH_UNKNOWN;
269 info->sector_count = 0;
270 info->size = 0;
271 }
272
273 /* Put FLASH back in read mode */
274 flash_reset(info);
275
276 return (info->size);
277}
278
279/*-----------------------------------------------------------------------
280 */
281
282int flash_erase (flash_info_t *info, int s_first, int s_last)
283{
284 vu_long *addr = (vu_long*)(info->start[0]);
285 int flag, prot, sect, l_sect;
286 ulong start, now, last;
287
288 debug ("flash_erase: first: %d last: %d\n", s_first, s_last);
289
290 if ((s_first < 0) || (s_first > s_last)) {
291 if (info->flash_id == FLASH_UNKNOWN) {
292 printf ("- missing\n");
293 } else {
294 printf ("- no sectors to erase\n");
295 }
296 return 1;
297 }
298
299 if ((info->flash_id == FLASH_UNKNOWN) ||
300 (info->flash_id > FLASH_AMD_COMP)) {
301 printf ("Can't erase unknown flash type %08lx - aborted\n",
302 info->flash_id);
303 return 1;
304 }
305
306 prot = 0;
307 for (sect=s_first; sect<=s_last; ++sect) {
308 if (info->protect[sect]) {
309 prot++;
310 }
311 }
312
313 if (prot) {
314 printf ("- Warning: %d protected sectors will not be erased!\n",
315 prot);
316 } else {
317 printf ("\n");
318 }
319
320 l_sect = -1;
321
322 /* Disable interrupts which might cause a timeout here */
323 flag = disable_interrupts();
324
325 addr[0x0555] = 0x00AA00AA;
326 addr[0x02AA] = 0x00550055;
327 addr[0x0555] = 0x00800080;
328 addr[0x0555] = 0x00AA00AA;
329 addr[0x02AA] = 0x00550055;
330
331 /* Start erase on unprotected sectors */
332 for (sect = s_first; sect<=s_last; sect++) {
333 if (info->protect[sect] == 0) { /* not protected */
334 addr = (vu_long*)(info->start[sect]);
335 addr[0] = 0x00300030;
336 l_sect = sect;
337 }
338 }
339
340 /* re-enable interrupts if necessary */
341 if (flag)
342 enable_interrupts();
343
344 /* wait at least 80us - let's wait 1 ms */
345 udelay (1000);
346
347 /*
348 * We wait for the last triggered sector
349 */
350 if (l_sect < 0)
351 goto DONE;
352
353 start = get_timer (0);
354 last = start;
355 addr = (vu_long*)(info->start[l_sect]);
356 while ((addr[0] & 0x00800080) != 0x00800080) {
357 if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
358 printf ("Timeout\n");
359 return 1;
360 }
361 /* show that we're waiting */
362 if ((now - last) > 1000) { /* every second */
363 putc ('.');
364 last = now;
365 }
366 }
367
368DONE:
369 /* reset to read mode */
370 addr = (volatile unsigned long *)info->start[0];
371 addr[0] = 0x00F000F0; /* reset bank */
372
373 printf (" done\n");
374 return 0;
375}
376
377/*-----------------------------------------------------------------------
378 * Copy memory to flash, returns:
379 * 0 - OK
380 * 1 - write timeout
381 * 2 - Flash not erased
382 */
383
384int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
385{
386 ulong cp, wp, data;
387 int i, l, rc;
388
389 /*
390 * Get lower word aligned address. Assumes 32 bit flash bus width.
391 */
392 wp = (addr & ~3);
393
394 /*
395 * handle unaligned start bytes
396 */
397 if ((l = addr - wp) != 0) {
398 data = 0;
399 for (i=0, cp=wp; i<l; ++i, ++cp) {
400 data = (data << 8) | (*(uchar *)cp);
401 }
402 for (; i<4 && cnt>0; ++i) {
403 data = (data << 8) | *src++;
404 --cnt;
405 ++cp;
406 }
407 for (; cnt==0 && i<4; ++i, ++cp) {
408 data = (data << 8) | (*(uchar *)cp);
409 }
410
411 if ((rc = write_word_amd(info, (FPW *)wp, data)) != 0) {
412 return (rc);
413 }
414 wp += 4;
415 }
416
417 /*
418 * handle word aligned part
419 */
420 while (cnt >= 4) {
421 data = 0;
422 for (i=0; i<4; ++i) {
423 data = (data << 8) | *src++;
424 }
425 if ((rc = write_word_amd(info, (FPW *)wp, data)) != 0) {
426 return (rc);
427 }
428 wp += 4;
429 cnt -= 4;
430 }
431
432 if (cnt == 0) {
433 return (0);
434 }
435
436 /*
437 * handle unaligned tail bytes
438 */
439 data = 0;
440 for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
441 data = (data << 8) | *src++;
442 --cnt;
443 }
444 for (; i<4; ++i, ++cp) {
445 data = (data << 8) | (*(uchar *)cp);
446 }
447
448 return (write_word_amd(info, (FPW *)wp, data));
449}
450
451/*-----------------------------------------------------------------------
452 * Write a word to Flash for AMD FLASH
453 * A word is 16 or 32 bits, whichever the bus width of the flash bank
454 * (not an individual chip) is.
455 *
456 * returns:
457 * 0 - OK
458 * 1 - write timeout
459 * 2 - Flash not erased
460 */
461static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
462{
463 ulong start;
464 int flag;
465 FPWV *base; /* first address in flash bank */
466
467 /* Check if Flash is (sufficiently) erased */
468 if ((*dest & data) != data) {
469 return (2);
470 }
471
472 base = (FPWV *)(info->start[0]);
473
474 /* Disable interrupts which might cause a timeout here */
475 flag = disable_interrupts();
476
477 base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
478 base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
479 base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */
480
481 *dest = data; /* start programming the data */
482
483 /* re-enable interrupts if necessary */
484 if (flag)
485 enable_interrupts();
486
487 start = get_timer (0);
488
489 /* data polling for D7 */
490 while ((*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
491 if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
492 *dest = (FPW)0x00F000F0; /* reset bank */
493 return (1);
494 }
495 }
496 return (0);
497}