Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2010-2012 |
| 4 | * NVIDIA Corporation <www.nvidia.com> |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
Tom Warren | bfcf46d | 2013-02-26 12:18:48 +0000 | [diff] [blame] | 7 | #ifndef _TEGRA_COMMON_H_ |
| 8 | #define _TEGRA_COMMON_H_ |
Alexey Brodkin | 1ace402 | 2014-02-26 17:47:58 +0400 | [diff] [blame] | 9 | #include <linux/sizes.h> |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 10 | #include <linux/stringify.h> |
| 11 | |
| 12 | /* |
| 13 | * High Level Configuration Options |
| 14 | */ |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 15 | #define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */ |
| 16 | |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 17 | #include <asm/arch/tegra.h> /* get chip and board defs */ |
| 18 | |
Thierry Reding | f41f0a1 | 2015-07-28 11:35:54 +0200 | [diff] [blame] | 19 | /* Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. */ |
| 20 | #ifndef CONFIG_ARM64 |
Rob Herring | 31df989 | 2013-10-04 10:22:47 -0500 | [diff] [blame] | 21 | #define CONFIG_SYS_TIMER_RATE 1000000 |
| 22 | #define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE |
Thierry Reding | f41f0a1 | 2015-07-28 11:35:54 +0200 | [diff] [blame] | 23 | #endif |
Rob Herring | 31df989 | 2013-10-04 10:22:47 -0500 | [diff] [blame] | 24 | |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 25 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 26 | |
| 27 | /* Environment */ |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 28 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */ |
| 29 | |
| 30 | /* |
Tom Warren | bfcf46d | 2013-02-26 12:18:48 +0000 | [diff] [blame] | 31 | * NS16550 Configuration |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 32 | */ |
Thomas Chou | 1874626 | 2015-11-19 21:48:11 +0800 | [diff] [blame] | 33 | #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 34 | |
| 35 | /* |
Stephen Warren | f175603 | 2014-04-18 10:56:11 -0600 | [diff] [blame] | 36 | * Common HW configuration. |
| 37 | * If this varies between SoCs later, move to tegraNN-common.h |
| 38 | * Note: This is number of devices, not max device ID. |
| 39 | */ |
| 40 | #define CONFIG_SYS_MMC_MAX_DEVICE 4 |
| 41 | |
| 42 | /* |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 43 | * select serial console configuration |
| 44 | */ |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 45 | |
| 46 | /* allow to overwrite serial and ethaddr */ |
| 47 | #define CONFIG_ENV_OVERWRITE |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 48 | |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 49 | /* turn on command-line edit/hist/auto */ |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 50 | |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 51 | /* |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 52 | * Increasing the size of the IO buffer as default nfsargs size is more |
| 53 | * than 256 and so it is not possible to edit it |
| 54 | */ |
Bryan Wu | 64a4fe7 | 2016-09-01 23:49:57 +0000 | [diff] [blame] | 55 | #define CONFIG_SYS_CBSIZE (1024 * 2) /* Console I/O Buffer Size */ |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 56 | /* Print Buffer Size */ |
Bryan Wu | 64a4fe7 | 2016-09-01 23:49:57 +0000 | [diff] [blame] | 57 | #define CONFIG_SYS_MAXARGS 64 /* max number of command args */ |
| 58 | |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 59 | /* Boot Argument Buffer Size */ |
| 60 | #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) |
| 61 | |
| 62 | #define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000) |
| 63 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000) |
| 64 | |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 65 | /*----------------------------------------------------------------------- |
| 66 | * Physical Memory Map |
| 67 | */ |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 68 | #define PHYS_SDRAM_1 NV_PA_SDRC_CS0 |
| 69 | #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */ |
| 70 | |
| 71 | #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE |
| 72 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
| 73 | |
| 74 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ |
| 75 | |
Stephen Warren | f097532 | 2017-12-19 18:30:37 -0700 | [diff] [blame] | 76 | #ifndef CONFIG_ARM64 |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 77 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE |
| 78 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN |
| 79 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ |
| 80 | CONFIG_SYS_INIT_RAM_SIZE - \ |
| 81 | GENERATED_GBL_DATA_SIZE) |
Stephen Warren | f097532 | 2017-12-19 18:30:37 -0700 | [diff] [blame] | 82 | #endif |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 83 | |
Stephen Warren | 0d1bd15 | 2017-12-19 18:30:35 -0700 | [diff] [blame] | 84 | #ifndef CONFIG_ARM64 |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 85 | /* Defines for SPL */ |
Albert ARIBAUD | 6ebc346 | 2013-04-12 05:14:30 +0000 | [diff] [blame] | 86 | #define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_TEXT_BASE - \ |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 87 | CONFIG_SPL_TEXT_BASE) |
| 88 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000 |
Stephen Warren | 0d1bd15 | 2017-12-19 18:30:35 -0700 | [diff] [blame] | 89 | #endif |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 90 | |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 91 | #endif /* _TEGRA_COMMON_H_ */ |