blob: ae7fc1c6304d4138a4475cae7b897a0cea1bb8d2 [file] [log] [blame]
Sam Protsenko3457bba2016-04-13 14:20:25 +03001config USB_DWC3
2 bool "DesignWare USB3 DRD Core Support"
Masahiro Yamada6ea247d2017-08-25 01:30:20 +09003 depends on USB_HOST || USB_GADGET
Sam Protsenko3457bba2016-04-13 14:20:25 +03004 help
5 Say Y here if your system has a Dual Role SuperSpeed
6 USB controller based on the DesignWare USB3 IP Core.
Sam Protsenko65403f32016-04-13 14:20:27 +03007
8if USB_DWC3
9
10choice
11 bool "DWC3 Mode Selection"
12
13config USB_DWC3_HOST
14 bool "Host only mode"
15 depends on USB
16 help
17 Select this when you want to use DWC3 in host mode only,
18 thereby the gadget feature will be regressed.
19
20config USB_DWC3_GADGET
21 bool "Gadget only mode"
22 depends on USB_GADGET
Masahiro Yamada6ea247d2017-08-25 01:30:20 +090023 select USB_GADGET_DUALSPEED
Sam Protsenko65403f32016-04-13 14:20:27 +030024 help
25 Select this when you want to use DWC3 in gadget mode only,
26 thereby the host feature will be regressed.
27
28endchoice
29
Sam Protsenkoc16bf622016-04-13 14:20:28 +030030comment "Platform Glue Driver Support"
31
32config USB_DWC3_OMAP
33 bool "Texas Instruments OMAP5 and similar Platforms"
34 help
35 Some platforms from Texas Instruments like OMAP5, DRA7xxx and
36 AM437x use this IP for USB2/3 functionality.
37
38 Say 'Y' here if you have one such device
39
Masahiro Yamadadc04b352017-09-28 22:01:00 +090040config USB_DWC3_UNIPHIER
41 bool "DesignWare USB3 Host Support on UniPhier Platforms"
42 depends on ARCH_UNIPHIER && USB_XHCI_DWC3
43 help
44 Support of USB2/3 functionality in Socionext UniPhier platforms.
45 Say 'Y' here if you have one such device.
46
Sam Protsenkob1427292016-04-13 14:20:29 +030047menu "PHY Subsystem"
48
49config USB_DWC3_PHY_OMAP
50 bool "TI OMAP SoC series USB DRD PHY driver"
51 help
52 Enable single driver for both USB2 PHY programming and USB3 PHY
53 programming for TI SoCs.
54
55config USB_DWC3_PHY_SAMSUNG
56 bool "Exynos5 SoC series USB DRD PHY driver"
57 help
58 Enable USB DRD PHY support for Exynos 5 SoC series.
59 This driver provides PHY interface for USB 3.0 DRD controller
60 present on Exynos5 SoC series.
61
62endmenu
63
Sam Protsenko65403f32016-04-13 14:20:27 +030064endif