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wdenke2211742002-11-02 23:30:20 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2002-2005
wdenke2211742002-11-02 23:30:20 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 *
26 * Configuration settings for the PCIPPC-2 board.
27 *
28 */
29
30/* ------------------------------------------------------------------------- */
31
32/*
33 * board/config.h - configuration options, board specific
34 */
35
36#ifndef __CONFIG_H
37#define __CONFIG_H
38
39/*
40 * High Level Configuration Options
41 * (easy to change)
42 */
43
44#define CONFIG_PCIPPC2 1 /* this is a PCIPPC2 board */
45
Wolfgang Denk2ae18242010-10-06 09:05:45 +020046#define CONFIG_SYS_TEXT_BASE 0xfff00000
47
wdenkc837dcb2004-01-20 23:12:12 +000048#define CONFIG_BOARD_EARLY_INIT_F 1
wdenke2211742002-11-02 23:30:20 +000049#define CONFIG_MISC_INIT_R 1
50
51#define CONFIG_CONS_INDEX 1
52#define CONFIG_BAUDRATE 9600
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenke2211742002-11-02 23:30:20 +000054
wdenke2211742002-11-02 23:30:20 +000055#define CONFIG_PREBOOT ""
56#define CONFIG_BOOTDELAY 5
57
Jon Loeliger18225e82007-07-09 21:31:24 -050058/*
59 * BOOTP options
60 */
61#define CONFIG_BOOTP_SUBNETMASK
62#define CONFIG_BOOTP_GATEWAY
63#define CONFIG_BOOTP_HOSTNAME
64#define CONFIG_BOOTP_BOOTPATH
65#define CONFIG_BOOTP_BOOTFILESIZE
wdenke2211742002-11-02 23:30:20 +000066
67#define CONFIG_MAC_PARTITION
68#define CONFIG_DOS_PARTITION
69
Jon Loeligeracf02692007-07-08 14:49:44 -050070
71/*
72 * Command line configuration.
73 */
74#include <config_cmd_default.h>
75
76#define CONFIG_CMD_ASKENV
77#define CONFIG_CMD_BSP
78#define CONFIG_CMD_DATE
79#define CONFIG_CMD_DHCP
Jon Loeligeracf02692007-07-08 14:49:44 -050080#define CONFIG_CMD_ELF
81#define CONFIG_CMD_NFS
82#define CONFIG_CMD_PCI
83#define CONFIG_CMD_SNTP
wdenke2211742002-11-02 23:30:20 +000084
85#define CONFIG_PCI 1
86#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
87
wdenke2211742002-11-02 23:30:20 +000088/*
89 * Miscellaneous configurable options
90 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#define CONFIG_SYS_LONGHELP /* undef to save memory */
92#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenke2211742002-11-02 23:30:20 +000093
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
95#ifdef CONFIG_SYS_HUSH_PARSER
96#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenke2211742002-11-02 23:30:20 +000097#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +000099
100/* Print Buffer Size
101 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
wdenke2211742002-11-02 23:30:20 +0000103
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_MAXARGS 64 /* max number of command args */
105#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
106#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
wdenke2211742002-11-02 23:30:20 +0000107
108/*-----------------------------------------------------------------------
109 * Start addresses for the final memory configuration
110 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenke2211742002-11-02 23:30:20 +0000112 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_SDRAM_BASE 0x00000000
114#define CONFIG_SYS_FLASH_BASE 0xFFF00000
115#define CONFIG_SYS_FLASH_MAX_SIZE 0x00100000
wdenke2211742002-11-02 23:30:20 +0000116/* Maximum amount of RAM.
117 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000 /* 512Mb */
wdenke2211742002-11-02 23:30:20 +0000119
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
wdenke2211742002-11-02 23:30:20 +0000121
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200122#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
wdenke2211742002-11-02 23:30:20 +0000123
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
125#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenke2211742002-11-02 23:30:20 +0000126
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_SDRAM_BASE && \
128 CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MAX_RAM_SIZE
129#define CONFIG_SYS_RAMBOOT
wdenke2211742002-11-02 23:30:20 +0000130#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#undef CONFIG_SYS_RAMBOOT
wdenke2211742002-11-02 23:30:20 +0000132#endif
133
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
135#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
wdenke2211742002-11-02 23:30:20 +0000136
137/*-----------------------------------------------------------------------
138 * Definitions for initial stack pointer and data area
139 */
140
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200142#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200143#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenke2211742002-11-02 23:30:20 +0000145
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_INIT_RAM_LOCK
wdenke2211742002-11-02 23:30:20 +0000147
148/*
149 * Temporary buffer for serial data until the real serial driver
150 * is initialised (memtest will destroy this buffer)
151 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_SCONSOLE_ADDR CONFIG_SYS_INIT_RAM_ADDR
153#define CONFIG_SYS_SCONSOLE_SIZE 0x0002000
wdenke2211742002-11-02 23:30:20 +0000154
155/* SDRAM 0 - 256MB
156 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
158#define CONFIG_SYS_DBAT0U (CONFIG_SYS_SDRAM_BASE | \
wdenke2211742002-11-02 23:30:20 +0000159 BATU_BL_256M | BATU_VS | BATU_VP)
160/* SDRAM 1 - 256MB
161 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_DBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | \
wdenke2211742002-11-02 23:30:20 +0000163 BATL_PP_10 | BATL_MEMCOHERENCE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_DBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | \
wdenke2211742002-11-02 23:30:20 +0000165 BATU_BL_256M | BATU_VS | BATU_VP)
166
167/* Init RAM in the CPU DCache (no backing memory)
168 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_DBAT2L (CONFIG_SYS_INIT_RAM_ADDR | \
wdenke2211742002-11-02 23:30:20 +0000170 BATL_PP_10 | BATL_MEMCOHERENCE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_DBAT2U (CONFIG_SYS_INIT_RAM_ADDR | \
wdenke2211742002-11-02 23:30:20 +0000172 BATU_BL_128K | BATU_VS | BATU_VP)
173
174/* I/O and PCI memory at 0xf0000000
175 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_DBAT3L (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
177#define CONFIG_SYS_DBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
wdenke2211742002-11-02 23:30:20 +0000178
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_IBAT0L CONFIG_SYS_DBAT0L
180#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
181#define CONFIG_SYS_IBAT1L CONFIG_SYS_DBAT1L
182#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
183#define CONFIG_SYS_IBAT2L CONFIG_SYS_DBAT2L
184#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
185#define CONFIG_SYS_IBAT3L CONFIG_SYS_DBAT3L
186#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
wdenke2211742002-11-02 23:30:20 +0000187
188/*
189 * Low Level Configuration Settings
190 * (address mappings, register initial values, etc.)
191 * You should know what you are doing if you make changes here.
192 * For the detail description refer to the PCIPPC2 user's manual.
193 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_HZ 1000
Wolfgang Denkee80fa72010-06-13 18:38:23 +0200195#define CONFIG_SYS_BUS_CLK 100000000 /* bus speed - 100 mhz */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_CPU_CLK 300000000
wdenke2211742002-11-02 23:30:20 +0000197
198/*
199 * For booting Linux, the board info and command line data
200 * have to be in the first 8 MB of memory, since this is
201 * the maximum mapped by the Linux kernel during initialization.
202 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenke2211742002-11-02 23:30:20 +0000204
205/*-----------------------------------------------------------------------
206 * FLASH organization
207 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
209#define CONFIG_SYS_MAX_FLASH_SECT 16 /* Max number of sectors in one bank */
wdenke2211742002-11-02 23:30:20 +0000210
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
212#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
wdenke2211742002-11-02 23:30:20 +0000213
214/*
215 * Note: environment is not EMBEDDED in the U-Boot code.
216 * It's stored in flash separately.
217 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200218#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x70000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200220#define CONFIG_ENV_SIZE 0x1000 /* Size of the Environment */
221#define CONFIG_ENV_SECT_SIZE 0x10000 /* Size of the Environment Sector */
wdenke2211742002-11-02 23:30:20 +0000222
223/*-----------------------------------------------------------------------
224 * Cache Configuration
225 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_CACHELINE_SIZE 32
Jon Loeligeracf02692007-07-08 14:49:44 -0500227#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenke2211742002-11-02 23:30:20 +0000229#endif
230
231/*
232 * L2 cache
233 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#undef CONFIG_SYS_L2
wdenke2211742002-11-02 23:30:20 +0000235#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
wdenk8bde7f72003-06-27 21:31:46 +0000236 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
wdenke2211742002-11-02 23:30:20 +0000237#define L2_ENABLE (L2_INIT | L2CR_L2E)
238
wdenke2211742002-11-02 23:30:20 +0000239/*-----------------------------------------------------------------------
wdenke2211742002-11-02 23:30:20 +0000240 RTC m48t59
241*/
242#define CONFIG_RTC_MK48T59
243
244#define CONFIG_WATCHDOG
245
wdenke2211742002-11-02 23:30:20 +0000246
247#define CONFIG_EEPRO100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
wdenke2211742002-11-02 23:30:20 +0000249#define CONFIG_TULIP
250
251#endif /* __CONFIG_H */