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Ilko Iliev32949232009-06-12 21:20:39 +02001/*
2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian.pop@leadtechdesign.com>
4 * Lead Tech Design <www.leadtechdesign.com>
5 * Ilko Iliev <www.ronetix.at>
6 *
7 * Configuation settings for the RONETIX PM9261 board.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
Asen Dimovf47316a2011-07-26 04:48:41 +000031/*
32 * SoC must be defined first, before hardware.h is included.
33 * In this case SoC is defined in boards.cfg.
34 */
35
36#include <asm/hardware.h>
Ilko Iliev32949232009-06-12 21:20:39 +020037/* ARM asynchronous clock */
Ilko Iliev32949232009-06-12 21:20:39 +020038
39#define CONFIG_DISPLAY_BOARDINFO
40
41#define MASTER_PLL_DIV 15
42#define MASTER_PLL_MUL 162
43#define MAIN_PLL_DIV 2
Asen Dimovf47316a2011-07-26 04:48:41 +000044#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
Achim Ehrlich7c966a82010-02-24 10:29:16 +010045#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
Ilko Iliev32949232009-06-12 21:20:39 +020046
47#define CONFIG_SYS_HZ 1000
48
Asen Dimovf47316a2011-07-26 04:48:41 +000049#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261"
Ilko Iliev32949232009-06-12 21:20:39 +020050#define CONFIG_PM9261 1 /* on a Ronetix PM9261 Board */
51#define CONFIG_ARCH_CPU_INIT
52#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
Asen Dimov4f81bf42010-12-12 12:41:30 +020053#define CONFIG_SYS_TEXT_BASE 0
Ilko Iliev32949232009-06-12 21:20:39 +020054
55/* clocks */
56/* CKGR_MOR - enable main osc. */
57#define CONFIG_SYS_MOR_VAL \
Asen Dimove3150c72010-04-06 16:18:04 +030058 (AT91_PMC_MOR_MOSCEN | \
Ilko Iliev32949232009-06-12 21:20:39 +020059 (255 << 8)) /* Main Oscillator Start-up Time */
60#define CONFIG_SYS_PLLAR_VAL \
Asen Dimove3150c72010-04-06 16:18:04 +030061 (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
62 AT91_PMC_PLLXR_OUT(3) | \
Ilko Iliev32949232009-06-12 21:20:39 +020063 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
64
65/* PCK/2 = MCK Master Clock from PLLA */
66#define CONFIG_SYS_MCKR1_VAL \
Asen Dimove3150c72010-04-06 16:18:04 +030067 (AT91_PMC_MCKR_CSS_SLOW | \
68 AT91_PMC_MCKR_PRES_1 | \
69 AT91_PMC_MCKR_MDIV_2 | \
70 AT91_PMC_MCKR_PLLADIV_1)
Ilko Iliev32949232009-06-12 21:20:39 +020071
72/* PCK/2 = MCK Master Clock from PLLA */
73#define CONFIG_SYS_MCKR2_VAL \
Asen Dimove3150c72010-04-06 16:18:04 +030074 (AT91_PMC_MCKR_CSS_PLLA | \
75 AT91_PMC_MCKR_PRES_1 | \
76 AT91_PMC_MCKR_MDIV_2 | \
77 AT91_PMC_MCKR_PLLADIV_1)
Ilko Iliev32949232009-06-12 21:20:39 +020078
79/* define PDC[31:16] as DATA[31:16] */
80#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
81/* no pull-up for D[31:16] */
82#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000
83
84/* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
85#define CONFIG_SYS_MATRIX_EBICSA_VAL \
Asen Dimove3150c72010-04-06 16:18:04 +030086 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A)
Ilko Iliev32949232009-06-12 21:20:39 +020087
88/* SDRAM */
89/* SDRAMC_MR Mode register */
90#define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL
91/* SDRAMC_TR - Refresh Timer register */
92#define CONFIG_SYS_SDRC_TR_VAL1 0x13C
93/* SDRAMC_CR - Configuration register*/
94#define CONFIG_SYS_SDRC_CR_VAL \
95 (AT91_SDRAMC_NC_9 | \
96 AT91_SDRAMC_NR_13 | \
97 AT91_SDRAMC_NB_4 | \
98 AT91_SDRAMC_CAS_3 | \
99 AT91_SDRAMC_DBW_32 | \
100 (1 << 8) | /* Write Recovery Delay */ \
101 (7 << 12) | /* Row Cycle Delay */ \
102 (3 << 16) | /* Row Precharge Delay */ \
103 (2 << 20) | /* Row to Column Delay */ \
104 (5 << 24) | /* Active to Precharge Delay */ \
105 (1 << 28)) /* Exit Self Refresh to Active Delay */
106
107/* Memory Device Register -> SDRAM */
108#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
109#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
110#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
111#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
112#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
113#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
114#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
115#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
116#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
117#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
118#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
119#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
120#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
121#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
122#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
123#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
124#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
125#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
126
127/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
128#define CONFIG_SYS_SMC0_SETUP0_VAL \
Asen Dimove3150c72010-04-06 16:18:04 +0300129 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
130 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
Ilko Iliev32949232009-06-12 21:20:39 +0200131#define CONFIG_SYS_SMC0_PULSE0_VAL \
Asen Dimove3150c72010-04-06 16:18:04 +0300132 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
133 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
Ilko Iliev32949232009-06-12 21:20:39 +0200134#define CONFIG_SYS_SMC0_CYCLE0_VAL \
Asen Dimove3150c72010-04-06 16:18:04 +0300135 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
Ilko Iliev32949232009-06-12 21:20:39 +0200136#define CONFIG_SYS_SMC0_MODE0_VAL \
Asen Dimove3150c72010-04-06 16:18:04 +0300137 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
138 AT91_SMC_MODE_DBW_16 | \
139 AT91_SMC_MODE_TDF | \
140 AT91_SMC_MODE_TDF_CYCLE(6))
Ilko Iliev32949232009-06-12 21:20:39 +0200141
142/* user reset enable */
143#define CONFIG_SYS_RSTC_RMR_VAL \
144 (AT91_RSTC_KEY | \
Asen Dimove3150c72010-04-06 16:18:04 +0300145 AT91_RSTC_CR_PROCRST | \
146 AT91_RSTC_MR_ERSTL(1) | \
147 AT91_RSTC_MR_ERSTL(2))
Ilko Iliev32949232009-06-12 21:20:39 +0200148
149/* Disable Watchdog */
150#define CONFIG_SYS_WDTC_WDMR_VAL \
Asen Dimove3150c72010-04-06 16:18:04 +0300151 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
152 AT91_WDT_MR_WDV(0xfff) | \
153 AT91_WDT_MR_WDDIS | \
154 AT91_WDT_MR_WDD(0xfff))
Ilko Iliev32949232009-06-12 21:20:39 +0200155
156#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
157#define CONFIG_SETUP_MEMORY_TAGS 1
158#define CONFIG_INITRD_TAG 1
159
160#undef CONFIG_SKIP_LOWLEVEL_INIT
Ilko Iliev32949232009-06-12 21:20:39 +0200161
162/*
163 * Hardware drivers
164 */
Jens Scharsigea8fbba2010-02-03 22:46:16 +0100165#define CONFIG_AT91_GPIO 1
Ilko Iliev32949232009-06-12 21:20:39 +0200166#define CONFIG_ATMEL_USART 1
Asen Dimovf47316a2011-07-26 04:48:41 +0000167#define CONFIG_USART_BASE ATMEL_BASE_DBGU
168#define CONFIG_USART_ID ATMEL_ID_SYS
Ilko Iliev32949232009-06-12 21:20:39 +0200169
170/* LCD */
171#define CONFIG_LCD 1
172#define LCD_BPP LCD_COLOR8
173#define CONFIG_LCD_LOGO 1
174#undef LCD_TEST_PATTERN
175#define CONFIG_LCD_INFO 1
176#define CONFIG_LCD_INFO_BELOW_LOGO 1
177#define CONFIG_SYS_WHITE_ON_BLACK 1
178#define CONFIG_ATMEL_LCD 1
179#define CONFIG_ATMEL_LCD_BGR555 1
180#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
181
182/* LED */
183#define CONFIG_AT91_LED
Asen Dimove3150c72010-04-06 16:18:04 +0300184#define CONFIG_RED_LED AT91_PIO_PORTC, 12
185#define CONFIG_GREEN_LED AT91_PIO_PORTC, 13
186#define CONFIG_YELLOW_LED AT91_PIO_PORTC, 15
Ilko Iliev32949232009-06-12 21:20:39 +0200187
188#define CONFIG_BOOTDELAY 3
189
190/*
191 * BOOTP options
192 */
193#define CONFIG_BOOTP_BOOTFILESIZE 1
194#define CONFIG_BOOTP_BOOTPATH 1
195#define CONFIG_BOOTP_GATEWAY 1
196#define CONFIG_BOOTP_HOSTNAME 1
197
198/*
199 * Command line configuration.
200 */
201#include <config_cmd_default.h>
202#undef CONFIG_CMD_BDI
203#undef CONFIG_CMD_IMI
Ilko Iliev32949232009-06-12 21:20:39 +0200204#undef CONFIG_CMD_FPGA
205#undef CONFIG_CMD_LOADS
206#undef CONFIG_CMD_IMLS
207
Asen Dimov6741b532010-12-12 12:41:36 +0200208#define CONFIG_CMD_CACHE
Ilko Iliev32949232009-06-12 21:20:39 +0200209#define CONFIG_CMD_PING 1
210#define CONFIG_CMD_DHCP 1
211#define CONFIG_CMD_NAND 1
212#define CONFIG_CMD_USB 1
213
214/* SDRAM */
215#define CONFIG_NR_DRAM_BANKS 1
216#define PHYS_SDRAM 0x20000000
217#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
218
219/* DataFlash */
220#define CONFIG_ATMEL_DATAFLASH_SPI
221#define CONFIG_HAS_DATAFLASH
222#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ)
223#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
224#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
225#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* CS3 */
226#define AT91_SPI_CLK 15000000
227#define DATAFLASH_TCSS (0x1a << 16)
228#define DATAFLASH_TCHS (0x1 << 24)
229
230/* NAND flash */
231#define CONFIG_NAND_ATMEL
232#define NAND_MAX_CHIPS 1
233#define CONFIG_SYS_MAX_NAND_DEVICE 1
234#define CONFIG_SYS_NAND_BASE 0x40000000
235#define CONFIG_SYS_NAND_DBW_8 1
236/* our ALE is AD22 */
237#define CONFIG_SYS_NAND_MASK_ALE (1 << 22)
238/* our CLE is AD21 */
239#define CONFIG_SYS_NAND_MASK_CLE (1 << 21)
Asen Dimove3150c72010-04-06 16:18:04 +0300240#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 14
241#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTA, 16
Ilko Iliev32949232009-06-12 21:20:39 +0200242
Ilko Iliev32949232009-06-12 21:20:39 +0200243/* NOR flash */
244#define CONFIG_SYS_FLASH_CFI 1
245#define CONFIG_FLASH_CFI_DRIVER 1
246#define PHYS_FLASH_1 0x10000000
247#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
248#define CONFIG_SYS_MAX_FLASH_SECT 256
249#define CONFIG_SYS_MAX_FLASH_BANKS 1
250
251/* Ethernet */
252#define CONFIG_DRIVER_DM9000 1
253#define CONFIG_DM9000_BASE 0x30000000
254#define DM9000_IO CONFIG_DM9000_BASE
255#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
256#define CONFIG_DM9000_USE_16BIT 1
257#define CONFIG_NET_RETRY_COUNT 20
258#define CONFIG_RESET_PHY_R 1
Ilko Iliev32949232009-06-12 21:20:39 +0200259
260/* USB */
261#define CONFIG_USB_ATMEL
262#define CONFIG_USB_OHCI_NEW 1
263#define CONFIG_DOS_PARTITION 1
264#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
265#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
266#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261"
267#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
268#define CONFIG_USB_STORAGE 1
269
270#define CONFIG_SYS_LOAD_ADDR 0x22000000
271
272#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
273#define CONFIG_SYS_MEMTEST_END 0x23e00000
274
275#undef CONFIG_SYS_USE_DATAFLASH_CS0
276#undef CONFIG_SYS_USE_NANDFLASH
277#define CONFIG_SYS_USE_FLASH 1
278
279#ifdef CONFIG_SYS_USE_DATAFLASH_CS0
280
281/* bootstrap + u-boot + env + linux in dataflash on CS0 */
282#define CONFIG_ENV_IS_IN_DATAFLASH 1
283#define CONFIG_SYS_MONITOR_BASE \
284 (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
285#define CONFIG_ENV_OFFSET 0x4200
286#define CONFIG_ENV_ADDR \
287 (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
288#define CONFIG_ENV_SIZE 0x4200
289#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
290#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
291 "root=/dev/mtdblock0 " \
Albin Tonnerre918319c2009-07-22 18:30:03 +0200292 "mtdparts=atmel_nand:-(root) " \
Ilko Iliev32949232009-06-12 21:20:39 +0200293 "rw rootfstype=jffs2"
294
295#elif defined(CONFIG_SYS_USE_NANDFLASH) /* CONFIG_SYS_USE_NANDFLASH */
296
297/* bootstrap + u-boot + env + linux in nandflash */
298#define CONFIG_ENV_IS_IN_NAND 1
299#define CONFIG_ENV_OFFSET 0x60000
300#define CONFIG_ENV_OFFSET_REDUND 0x80000
301#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
302#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
303#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
304 "root=/dev/mtdblock5 " \
Albin Tonnerre918319c2009-07-22 18:30:03 +0200305 "mtdparts=atmel_nand:128k(bootstrap)ro," \
Ilko Iliev32949232009-06-12 21:20:39 +0200306 "256k(uboot)ro,128k(env1)ro," \
307 "128k(env2)ro,2M(linux),-(root) " \
308 "rw rootfstype=jffs2"
309
310#elif defined (CONFIG_SYS_USE_FLASH)
311
312#define CONFIG_ENV_IS_IN_FLASH 1
313#define CONFIG_ENV_OFFSET 0x40000
314#define CONFIG_ENV_SECT_SIZE 0x10000
315#define CONFIG_ENV_SIZE 0x10000
316#define CONFIG_ENV_OVERWRITE 1
317
318/* JFFS Partition offset set */
319#define CONFIG_SYS_JFFS2_FIRST_BANK 0
320#define CONFIG_SYS_JFFS2_NUM_BANKS 1
321
322/* 512k reserved for u-boot */
323#define CONFIG_SYS_JFFS2_FIRST_SECTOR 11
324
325#define CONFIG_BOOTCOMMAND "run flashboot"
326
327#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=nand"
328#define MTDPARTS_DEFAULT \
329 "mtdparts=physmap-flash.0:" \
330 "256k(u-boot)ro," \
331 "64k(u-boot-env)ro," \
332 "1408k(kernel)," \
333 "-(rootfs);" \
334 "nand:-(nand)"
335
336#define CONFIG_CON_ROT "fbcon=rotate:3 "
337#define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 " CONFIG_CON_ROT
338
339#define CONFIG_EXTRA_ENV_SETTINGS \
340 "mtdids=" MTDIDS_DEFAULT "\0" \
341 "mtdparts=" MTDPARTS_DEFAULT "\0" \
342 "partition=nand0,0\0" \
343 "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
344 "nfsargs=setenv bootargs root=/dev/nfs rw " \
345 CONFIG_CON_ROT \
346 "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \
347 "addip=setenv bootargs $(bootargs) " \
348 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
349 ":$(hostname):eth0:off\0" \
350 "ramboot=tftpboot 0x22000000 vmImage;" \
351 "run ramargs;run addip;bootm 22000000\0" \
352 "nfsboot=tftpboot 0x22000000 vmImage;" \
353 "run nfsargs;run addip;bootm 22000000\0" \
354 "flashboot=run ramargs;run addip;bootm 0x10050000\0" \
355 ""
356#else
357#error "Undefined memory device"
358#endif
359
360#define CONFIG_BAUDRATE 115200
361#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
362
363#define CONFIG_SYS_PROMPT "pm9261> "
364#define CONFIG_SYS_CBSIZE 256
365#define CONFIG_SYS_MAXARGS 16
366#define CONFIG_SYS_PBSIZE \
367 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
368#define CONFIG_SYS_LONGHELP 1
369#define CONFIG_CMDLINE_EDITING 1
370
Ilko Iliev32949232009-06-12 21:20:39 +0200371/*
372 * Size of malloc() pool
373 */
374#define CONFIG_SYS_MALLOC_LEN \
375 ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
Ilko Iliev32949232009-06-12 21:20:39 +0200376
Asen Dimov4f81bf42010-12-12 12:41:30 +0200377#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
378#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
379 GENERATED_GBL_DATA_SIZE)
380
Ilko Iliev32949232009-06-12 21:20:39 +0200381#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
382
383#ifdef CONFIG_USE_IRQ
384#error CONFIG_USE_IRQ not supported
385#endif
386
387#endif