| Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Ludovic Desroches | aaa4ba9 | 2017-11-17 14:57:12 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Configuration file for the SAMA5D2 PTC EK Board. |
| 4 | * |
| 5 | * Copyright (C) 2017 Microchip Technology Inc. |
| 6 | * Wenyou Yang <wenyou.yang@microchip.com> |
| 7 | * Ludovic Desroches <ludovic.desroches@microchip.com> |
| Ludovic Desroches | aaa4ba9 | 2017-11-17 14:57:12 +0800 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #ifndef __CONFIG_H |
| 11 | #define __CONFIG_H |
| 12 | |
| 13 | #include "at91-sama5_common.h" |
| 14 | |
| 15 | #undef CONFIG_SYS_AT91_MAIN_CLOCK |
| 16 | #define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ |
| 17 | |
| Ludovic Desroches | aaa4ba9 | 2017-11-17 14:57:12 +0800 | [diff] [blame] | 18 | /* SDRAM */ |
| Ludovic Desroches | aaa4ba9 | 2017-11-17 14:57:12 +0800 | [diff] [blame] | 19 | #define CONFIG_SYS_SDRAM_BASE 0x20000000 |
| 20 | #define CONFIG_SYS_SDRAM_SIZE 0x20000000 |
| 21 | |
| 22 | #define CONFIG_SYS_INIT_SP_ADDR \ |
| 23 | (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) |
| 24 | |
| 25 | #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ |
| 26 | |
| 27 | /* NAND Flash */ |
| 28 | #ifdef CONFIG_CMD_NAND |
| Ludovic Desroches | aaa4ba9 | 2017-11-17 14:57:12 +0800 | [diff] [blame] | 29 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 30 | #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 |
| 31 | /* our ALE is AD21 */ |
| 32 | #define CONFIG_SYS_NAND_MASK_ALE BIT(21) |
| 33 | /* our CLE is AD22 */ |
| 34 | #define CONFIG_SYS_NAND_MASK_CLE BIT(22) |
| 35 | #define CONFIG_SYS_NAND_ONFI_DETECTION |
| Ludovic Desroches | aaa4ba9 | 2017-11-17 14:57:12 +0800 | [diff] [blame] | 36 | #endif |
| 37 | |
| 38 | #endif /* __CONFIG_H */ |