Enric Balletbo i Serra | 9a878e8 | 2018-12-28 11:55:48 +0100 | [diff] [blame] | 1 | /* |
| 2 | * am335x-igep0033.dtsi - Device Tree file for IGEP COM AQUILA AM335x |
| 3 | * |
| 4 | * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | */ |
| 10 | |
| 11 | /dts-v1/; |
| 12 | |
| 13 | #include "am33xx.dtsi" |
| 14 | #include <dt-bindings/interrupt-controller/irq.h> |
| 15 | |
| 16 | / { |
| 17 | cpus { |
| 18 | cpu@0 { |
| 19 | cpu0-supply = <&vdd1_reg>; |
| 20 | }; |
| 21 | }; |
| 22 | |
| 23 | memory@80000000 { |
| 24 | device_type = "memory"; |
| 25 | reg = <0x80000000 0x10000000>; /* 256 MB */ |
| 26 | }; |
| 27 | |
| 28 | leds { |
| 29 | pinctrl-names = "default"; |
| 30 | pinctrl-0 = <&leds_pins>; |
| 31 | |
| 32 | compatible = "gpio-leds"; |
| 33 | |
| 34 | led0 { |
| 35 | label = "com:green:user"; |
| 36 | gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; |
| 37 | default-state = "on"; |
| 38 | }; |
| 39 | }; |
| 40 | |
| 41 | vbat: fixedregulator0 { |
| 42 | compatible = "regulator-fixed"; |
| 43 | regulator-name = "vbat"; |
| 44 | regulator-min-microvolt = <5000000>; |
| 45 | regulator-max-microvolt = <5000000>; |
| 46 | regulator-boot-on; |
| 47 | }; |
| 48 | |
| 49 | vmmc: fixedregulator1 { |
| 50 | compatible = "regulator-fixed"; |
| 51 | regulator-name = "vmmc"; |
| 52 | regulator-min-microvolt = <3300000>; |
| 53 | regulator-max-microvolt = <3300000>; |
| 54 | }; |
| 55 | }; |
| 56 | |
| 57 | &am33xx_pinmux { |
| 58 | i2c0_pins: pinmux_i2c0_pins { |
| 59 | pinctrl-single,pins = < |
| 60 | AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ |
| 61 | AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ |
| 62 | >; |
| 63 | }; |
| 64 | |
| 65 | nandflash_pins: pinmux_nandflash_pins { |
| 66 | pinctrl-single,pins = < |
| 67 | AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ |
| 68 | AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ |
| 69 | AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ |
| 70 | AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ |
| 71 | AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ |
| 72 | AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ |
| 73 | AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ |
| 74 | AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ |
| 75 | AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ |
| 76 | AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */ |
| 77 | AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ |
| 78 | AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ |
| 79 | AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ |
| 80 | AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ |
| 81 | AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ |
| 82 | >; |
| 83 | }; |
| 84 | |
| 85 | uart0_pins: pinmux_uart0_pins { |
| 86 | pinctrl-single,pins = < |
| 87 | AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ |
| 88 | AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ |
| 89 | >; |
| 90 | }; |
| 91 | |
| 92 | leds_pins: pinmux_leds_pins { |
| 93 | pinctrl-single,pins = < |
| 94 | AM33XX_IOPAD(0x85c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */ |
| 95 | >; |
| 96 | }; |
| 97 | }; |
| 98 | |
| 99 | &mac { |
| 100 | status = "okay"; |
| 101 | }; |
| 102 | |
| 103 | &davinci_mdio { |
| 104 | status = "okay"; |
Grygorii Strashko | 3b3e8a3 | 2019-08-31 10:30:34 +0300 | [diff] [blame] | 105 | |
| 106 | ethphy0: ethernet-phy@0 { |
| 107 | reg = <0>; |
| 108 | }; |
| 109 | |
| 110 | ethphy1: ethernet-phy@1 { |
| 111 | reg = <1>; |
| 112 | }; |
Enric Balletbo i Serra | 9a878e8 | 2018-12-28 11:55:48 +0100 | [diff] [blame] | 113 | }; |
| 114 | |
| 115 | &cpsw_emac0 { |
Grygorii Strashko | 3b3e8a3 | 2019-08-31 10:30:34 +0300 | [diff] [blame] | 116 | phy-handle = <ðphy0>; |
Enric Balletbo i Serra | 9a878e8 | 2018-12-28 11:55:48 +0100 | [diff] [blame] | 117 | phy-mode = "rmii"; |
| 118 | }; |
| 119 | |
| 120 | &cpsw_emac1 { |
Grygorii Strashko | 3b3e8a3 | 2019-08-31 10:30:34 +0300 | [diff] [blame] | 121 | phy-handle = <ðphy1>; |
Enric Balletbo i Serra | 9a878e8 | 2018-12-28 11:55:48 +0100 | [diff] [blame] | 122 | phy-mode = "rmii"; |
| 123 | }; |
| 124 | |
| 125 | &phy_sel { |
| 126 | rmii-clock-ext; |
| 127 | }; |
| 128 | |
| 129 | &elm { |
| 130 | status = "okay"; |
| 131 | }; |
| 132 | |
| 133 | &gpmc { |
| 134 | status = "okay"; |
| 135 | pinctrl-names = "default"; |
| 136 | pinctrl-0 = <&nandflash_pins>; |
| 137 | |
| 138 | ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ |
| 139 | |
| 140 | nand@0,0 { |
| 141 | compatible = "ti,omap2-nand"; |
| 142 | reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ |
| 143 | interrupt-parent = <&gpmc>; |
| 144 | interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ |
| 145 | <1 IRQ_TYPE_NONE>; /* termcount */ |
| 146 | rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ |
| 147 | nand-bus-width = <8>; |
| 148 | ti,nand-ecc-opt = "bch8"; |
| 149 | gpmc,device-width = <1>; |
| 150 | gpmc,sync-clk-ps = <0>; |
| 151 | gpmc,cs-on-ns = <0>; |
| 152 | gpmc,cs-rd-off-ns = <44>; |
| 153 | gpmc,cs-wr-off-ns = <44>; |
| 154 | gpmc,adv-on-ns = <6>; |
| 155 | gpmc,adv-rd-off-ns = <34>; |
| 156 | gpmc,adv-wr-off-ns = <44>; |
| 157 | gpmc,we-on-ns = <0>; |
| 158 | gpmc,we-off-ns = <40>; |
| 159 | gpmc,oe-on-ns = <0>; |
| 160 | gpmc,oe-off-ns = <54>; |
| 161 | gpmc,access-ns = <64>; |
| 162 | gpmc,rd-cycle-ns = <82>; |
| 163 | gpmc,wr-cycle-ns = <82>; |
| 164 | gpmc,bus-turnaround-ns = <0>; |
| 165 | gpmc,cycle2cycle-delay-ns = <0>; |
| 166 | gpmc,clk-activation-ns = <0>; |
| 167 | gpmc,wr-access-ns = <40>; |
| 168 | gpmc,wr-data-mux-bus-ns = <0>; |
| 169 | |
| 170 | #address-cells = <1>; |
| 171 | #size-cells = <1>; |
| 172 | ti,elm-id = <&elm>; |
| 173 | |
| 174 | /* MTD partition table */ |
| 175 | partition@0 { |
| 176 | label = "SPL"; |
| 177 | reg = <0x00000000 0x000080000>; |
| 178 | }; |
| 179 | |
| 180 | partition@1 { |
| 181 | label = "U-boot"; |
| 182 | reg = <0x00080000 0x001e0000>; |
| 183 | }; |
| 184 | |
| 185 | partition@2 { |
| 186 | label = "U-Boot Env"; |
| 187 | reg = <0x00260000 0x00020000>; |
| 188 | }; |
| 189 | |
| 190 | partition@3 { |
| 191 | label = "Kernel"; |
| 192 | reg = <0x00280000 0x00500000>; |
| 193 | }; |
| 194 | |
| 195 | partition@4 { |
| 196 | label = "File System"; |
| 197 | reg = <0x00780000 0x007880000>; |
| 198 | }; |
| 199 | }; |
| 200 | }; |
| 201 | |
| 202 | &i2c0 { |
| 203 | status = "okay"; |
| 204 | pinctrl-names = "default"; |
| 205 | pinctrl-0 = <&i2c0_pins>; |
| 206 | |
| 207 | clock-frequency = <400000>; |
| 208 | |
| 209 | tps: tps@2d { |
| 210 | reg = <0x2d>; |
| 211 | }; |
| 212 | }; |
| 213 | |
| 214 | &mmc1 { |
| 215 | status = "okay"; |
| 216 | vmmc-supply = <&vmmc>; |
| 217 | bus-width = <4>; |
| 218 | }; |
| 219 | |
| 220 | &uart0 { |
| 221 | status = "okay"; |
| 222 | pinctrl-names = "default"; |
| 223 | pinctrl-0 = <&uart0_pins>; |
| 224 | }; |
| 225 | |
| 226 | &usb { |
| 227 | status = "okay"; |
| 228 | }; |
| 229 | |
| 230 | &usb_ctrl_mod { |
| 231 | status = "okay"; |
| 232 | }; |
| 233 | |
| 234 | &usb0_phy { |
| 235 | status = "okay"; |
| 236 | }; |
| 237 | |
| 238 | &usb1_phy { |
| 239 | status = "okay"; |
| 240 | }; |
| 241 | |
| 242 | &usb0 { |
| 243 | status = "okay"; |
| 244 | }; |
| 245 | |
| 246 | &usb1 { |
| 247 | status = "okay"; |
| 248 | dr_mode = "host"; |
| 249 | }; |
| 250 | |
| 251 | &cppi41dma { |
| 252 | status = "okay"; |
| 253 | }; |
| 254 | |
| 255 | #include "tps65910.dtsi" |
| 256 | |
| 257 | &tps { |
| 258 | vcc1-supply = <&vbat>; |
| 259 | vcc2-supply = <&vbat>; |
| 260 | vcc3-supply = <&vbat>; |
| 261 | vcc4-supply = <&vbat>; |
| 262 | vcc5-supply = <&vbat>; |
| 263 | vcc6-supply = <&vbat>; |
| 264 | vcc7-supply = <&vbat>; |
| 265 | vccio-supply = <&vbat>; |
| 266 | |
| 267 | regulators { |
| 268 | vrtc_reg: regulator@0 { |
| 269 | regulator-always-on; |
| 270 | }; |
| 271 | |
| 272 | vio_reg: regulator@1 { |
| 273 | regulator-always-on; |
| 274 | }; |
| 275 | |
| 276 | vdd1_reg: regulator@2 { |
| 277 | /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ |
| 278 | regulator-name = "vdd_mpu"; |
| 279 | regulator-min-microvolt = <912500>; |
| 280 | regulator-max-microvolt = <1312500>; |
| 281 | regulator-boot-on; |
| 282 | regulator-always-on; |
| 283 | }; |
| 284 | |
| 285 | vdd2_reg: regulator@3 { |
| 286 | /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ |
| 287 | regulator-name = "vdd_core"; |
| 288 | regulator-min-microvolt = <912500>; |
| 289 | regulator-max-microvolt = <1150000>; |
| 290 | regulator-boot-on; |
| 291 | regulator-always-on; |
| 292 | }; |
| 293 | |
| 294 | vdd3_reg: regulator@4 { |
| 295 | regulator-always-on; |
| 296 | }; |
| 297 | |
| 298 | vdig1_reg: regulator@5 { |
| 299 | regulator-always-on; |
| 300 | }; |
| 301 | |
| 302 | vdig2_reg: regulator@6 { |
| 303 | regulator-always-on; |
| 304 | }; |
| 305 | |
| 306 | vpll_reg: regulator@7 { |
| 307 | regulator-always-on; |
| 308 | }; |
| 309 | |
| 310 | vdac_reg: regulator@8 { |
| 311 | regulator-always-on; |
| 312 | }; |
| 313 | |
| 314 | vaux1_reg: regulator@9 { |
| 315 | regulator-always-on; |
| 316 | }; |
| 317 | |
| 318 | vaux2_reg: regulator@10 { |
| 319 | regulator-always-on; |
| 320 | }; |
| 321 | |
| 322 | vaux33_reg: regulator@11 { |
| 323 | regulator-always-on; |
| 324 | }; |
| 325 | |
| 326 | vmmc_reg: regulator@12 { |
| 327 | regulator-always-on; |
| 328 | }; |
| 329 | }; |
| 330 | }; |
| 331 | |