| Giulio Benetti | 8d9c076 | 2020-01-10 15:51:48 +0100 | [diff] [blame^] | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) |
| 2 | /* |
| 3 | * Copyright (C) 2019 |
| 4 | * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> |
| 5 | */ |
| 6 | |
| 7 | /dts-v1/; |
| 8 | #include "imxrt1050.dtsi" |
| 9 | #include "imxrt1050-evk-u-boot.dtsi" |
| 10 | #include <dt-bindings/pinctrl/pins-imxrt1050.h> |
| 11 | |
| 12 | / { |
| 13 | model = "NXP IMXRT1050-evk board"; |
| 14 | compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050"; |
| 15 | |
| 16 | chosen { |
| 17 | bootargs = "root=/dev/ram"; |
| 18 | stdout-path = "serial0:115200n8"; |
| 19 | }; |
| 20 | |
| 21 | memory { |
| 22 | reg = <0x80000000 0x2000000>; |
| 23 | }; |
| 24 | }; |
| 25 | |
| 26 | &lpuart1 { /* console */ |
| 27 | pinctrl-names = "default"; |
| 28 | pinctrl-0 = <&pinctrl_lpuart1>; |
| 29 | status = "okay"; |
| 30 | }; |
| 31 | |
| 32 | &semc { |
| 33 | /* |
| 34 | * Memory configuration from sdram datasheet IS42S16160J-6BLI |
| 35 | */ |
| 36 | fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8 |
| 37 | MUX_CSX0_SDRAM_CS1 |
| 38 | 0 |
| 39 | 0 |
| 40 | 0 |
| 41 | 0>; |
| 42 | fsl,sdram-control = /bits/ 8 <MEM_WIDTH_16BITS |
| 43 | BL_8 |
| 44 | COL_9BITS |
| 45 | CL_3>; |
| 46 | fsl,sdram-timing = /bits/ 8 <0x2 |
| 47 | 0x2 |
| 48 | 0x9 |
| 49 | 0x1 |
| 50 | 0x5 |
| 51 | 0x6 |
| 52 | |
| 53 | 0x20 |
| 54 | 0x09 |
| 55 | 0x01 |
| 56 | 0x00 |
| 57 | |
| 58 | 0x04 |
| 59 | 0x0A |
| 60 | 0x21 |
| 61 | 0x50>; |
| 62 | |
| 63 | bank1: bank@0 { |
| 64 | fsl,base-address = <0x80000000>; |
| 65 | fsl,memory-size = <MEM_SIZE_32M>; |
| 66 | }; |
| 67 | }; |
| 68 | |
| 69 | &iomuxc { |
| 70 | pinctrl-names = "default"; |
| 71 | pinctrl-0 = <&pinctrl_lpuart1>; |
| 72 | |
| 73 | imxrt1050-evk { |
| 74 | pinctrl_lpuart1: lpuart1grp { |
| 75 | fsl,pins = < |
| 76 | MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD |
| 77 | 0xf1 |
| 78 | MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD |
| 79 | 0xf1 |
| 80 | >; |
| 81 | }; |
| 82 | |
| 83 | pinctrl_semc: semcgrp { |
| 84 | fsl,pins = < |
| 85 | MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 |
| 86 | 0xf1 /* SEMC_D0 */ |
| 87 | MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 |
| 88 | 0xf1 /* SEMC_D1 */ |
| 89 | MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02 |
| 90 | 0xf1 /* SEMC_D2 */ |
| 91 | MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03 |
| 92 | 0xf1 /* SEMC_D3 */ |
| 93 | MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04 |
| 94 | 0xf1 /* SEMC_D4 */ |
| 95 | MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05 |
| 96 | 0xf1 /* SEMC_D5 */ |
| 97 | MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06 |
| 98 | 0xf1 /* SEMC_D6 */ |
| 99 | MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07 |
| 100 | 0xf1 /* SEMC_D7 */ |
| 101 | MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00 |
| 102 | 0xf1 /* SEMC_DM0 */ |
| 103 | MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00 |
| 104 | 0xf1 /* SEMC_A0 */ |
| 105 | MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01 |
| 106 | 0xf1 /* SEMC_A1 */ |
| 107 | MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02 |
| 108 | 0xf1 /* SEMC_A2 */ |
| 109 | MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03 |
| 110 | 0xf1 /* SEMC_A3 */ |
| 111 | MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04 |
| 112 | 0xf1 /* SEMC_A4 */ |
| 113 | MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05 |
| 114 | 0xf1 /* SEMC_A5 */ |
| 115 | MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06 |
| 116 | 0xf1 /* SEMC_A6 */ |
| 117 | MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07 |
| 118 | 0xf1 /* SEMC_A7 */ |
| 119 | MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08 |
| 120 | 0xf1 /* SEMC_A8 */ |
| 121 | MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09 |
| 122 | 0xf1 /* SEMC_A9 */ |
| 123 | MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11 |
| 124 | 0xf1 /* SEMC_A11 */ |
| 125 | MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12 |
| 126 | 0xf1 /* SEMC_A12 */ |
| 127 | MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0 |
| 128 | 0xf1 /* SEMC_BA0 */ |
| 129 | MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1 |
| 130 | 0xf1 /* SEMC_BA1 */ |
| 131 | MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10 |
| 132 | 0xf1 /* SEMC_A10 */ |
| 133 | MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS |
| 134 | 0xf1 /* SEMC_CAS */ |
| 135 | MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS |
| 136 | 0xf1 /* SEMC_RAS */ |
| 137 | MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK |
| 138 | 0xf1 /* SEMC_CLK */ |
| 139 | MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE |
| 140 | 0xf1 /* SEMC_CKE */ |
| 141 | MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE |
| 142 | 0xf1 /* SEMC_WE */ |
| 143 | MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0 |
| 144 | 0xf1 /* SEMC_CS0 */ |
| 145 | MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08 |
| 146 | 0xf1 /* SEMC_D8 */ |
| 147 | MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09 |
| 148 | 0xf1 /* SEMC_D9 */ |
| 149 | MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10 |
| 150 | 0xf1 /* SEMC_D10 */ |
| 151 | MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11 |
| 152 | 0xf1 /* SEMC_D11 */ |
| 153 | MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12 |
| 154 | 0xf1 /* SEMC_D12 */ |
| 155 | MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13 |
| 156 | 0xf1 /* SEMC_D13 */ |
| 157 | MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14 |
| 158 | 0xf1 /* SEMC_D14 */ |
| 159 | MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15 |
| 160 | 0xf1 /* SEMC_D15 */ |
| 161 | MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01 |
| 162 | 0xf1 /* SEMC_DM1 */ |
| 163 | MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS |
| 164 | (IMX_PAD_SION | 0xf1) /* SEMC_DQS */ |
| 165 | >; |
| 166 | }; |
| 167 | |
| 168 | pinctrl_usdhc0: usdhc0grp { |
| 169 | fsl,pins = < |
| 170 | MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B |
| 171 | 0x1B000 |
| 172 | MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT |
| 173 | 0xB069 |
| 174 | MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD |
| 175 | 0x17061 |
| 176 | MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK |
| 177 | 0x17061 |
| 178 | MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 |
| 179 | 0x17061 |
| 180 | MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 |
| 181 | 0x17061 |
| 182 | MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 |
| 183 | 0x17061 |
| 184 | MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 |
| 185 | 0x17061 |
| 186 | >; |
| 187 | }; |
| 188 | }; |
| 189 | }; |
| 190 | |
| 191 | &usdhc1 { |
| 192 | pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; |
| 193 | pinctrl-0 = <&pinctrl_usdhc0>; |
| 194 | pinctrl-1 = <&pinctrl_usdhc0>; |
| 195 | pinctrl-2 = <&pinctrl_usdhc0>; |
| 196 | pinctrl-3 = <&pinctrl_usdhc0>; |
| 197 | status = "okay"; |
| 198 | |
| 199 | cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; |
| 200 | }; |