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Miquel Raynala430fa02018-08-16 17:30:07 +02001
Miquel Raynal88718be2019-10-03 19:50:03 +02002menuconfig MTD_RAW_NAND
Miquel Raynal3657b2f2018-08-16 17:30:08 +02003 bool "Raw NAND Device Support"
Miquel Raynal88718be2019-10-03 19:50:03 +02004if MTD_RAW_NAND
Miquel Raynala430fa02018-08-16 17:30:07 +02005
6config SYS_NAND_SELF_INIT
7 bool
8 help
9 This option, if enabled, provides more flexible and linux-like
10 NAND initialization process.
11
Stefan Agnera38c3af2018-12-06 14:57:09 +010012config SYS_NAND_DRIVER_ECC_LAYOUT
13 bool
14 help
15 Omit standard ECC layouts to safe space. Select this if your driver
16 is known to provide its own ECC layout.
17
Stefan Roesec680df72019-08-22 12:28:04 +020018config SYS_NAND_USE_FLASH_BBT
19 bool "Enable BBT (Bad Block Table) support"
20 help
21 Enable the BBT (Bad Block Table) usage.
22
Miquel Raynala430fa02018-08-16 17:30:07 +020023config NAND_ATMEL
24 bool "Support Atmel NAND controller"
25 imply SYS_NAND_USE_FLASH_BBT
26 help
27 Enable this driver for NAND flash platforms using an Atmel NAND
28 controller.
29
Derald D. Woods49ad4022018-12-15 01:36:46 -060030if NAND_ATMEL
31
32config ATMEL_NAND_HWECC
33 bool "Atmel Hardware ECC"
Derald D. Woods49ad4022018-12-15 01:36:46 -060034
35config ATMEL_NAND_HW_PMECC
36 bool "Atmel Programmable Multibit ECC (PMECC)"
37 select ATMEL_NAND_HWECC
Derald D. Woods49ad4022018-12-15 01:36:46 -060038 help
39 The Programmable Multibit ECC (PMECC) controller is a programmable
40 binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder.
41
42config PMECC_CAP
43 int "PMECC Correctable ECC Bits"
44 depends on ATMEL_NAND_HW_PMECC
45 default 2
46 help
47 Correctable ECC bits, can be 2, 4, 8, 12, and 24.
48
49config PMECC_SECTOR_SIZE
50 int "PMECC Sector Size"
51 depends on ATMEL_NAND_HW_PMECC
52 default 512
53 help
54 Sector size, in bytes, can be 512 or 1024.
55
56config SPL_GENERATE_ATMEL_PMECC_HEADER
57 bool "Atmel PMECC Header Generation"
58 select ATMEL_NAND_HWECC
59 select ATMEL_NAND_HW_PMECC
Derald D. Woods49ad4022018-12-15 01:36:46 -060060 help
61 Generate Programmable Multibit ECC (PMECC) header for SPL image.
62
63endif
64
Philippe Reynes22daafb2019-03-15 15:14:36 +010065config NAND_BRCMNAND
66 bool "Support Broadcom NAND controller"
Miquel Raynal1de770d2019-10-03 19:50:04 +020067 depends on OF_CONTROL && DM && DM_MTD
Philippe Reynes22daafb2019-03-15 15:14:36 +010068 help
69 Enable the driver for NAND flash on platforms using a Broadcom NAND
70 controller.
71
Álvaro Fernández Rojasa9f80cf2019-08-28 19:12:15 +020072config NAND_BRCMNAND_6368
73 bool "Support Broadcom NAND controller on bcm6368"
74 depends on NAND_BRCMNAND && ARCH_BMIPS
75 help
76 Enable support for broadcom nand driver on bcm6368.
77
Philippe Reynes14533012020-01-07 20:14:13 +010078config NAND_BRCMNAND_68360
79 bool "Support Broadcom NAND controller on bcm68360"
80 depends on NAND_BRCMNAND && ARCH_BCM68360
81 help
82 Enable support for broadcom nand driver on bcm68360.
83
Philippe Reynes22daafb2019-03-15 15:14:36 +010084config NAND_BRCMNAND_6838
85 bool "Support Broadcom NAND controller on bcm6838"
86 depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838
87 help
88 Enable support for broadcom nand driver on bcm6838.
89
90config NAND_BRCMNAND_6858
91 bool "Support Broadcom NAND controller on bcm6858"
92 depends on NAND_BRCMNAND && ARCH_BCM6858
93 help
94 Enable support for broadcom nand driver on bcm6858.
95
96config NAND_BRCMNAND_63158
97 bool "Support Broadcom NAND controller on bcm63158"
98 depends on NAND_BRCMNAND && ARCH_BCM63158
99 help
100 Enable support for broadcom nand driver on bcm63158.
101
Miquel Raynala430fa02018-08-16 17:30:07 +0200102config NAND_DAVINCI
103 bool "Support TI Davinci NAND controller"
104 help
105 Enable this driver for NAND flash controllers available in TI Davinci
106 and Keystone2 platforms
107
Tom Rinic8c934b2021-09-12 20:32:24 -0400108config KEYSTONE_RBL_NAND
109 depends on ARCH_KEYSTONE
110 def_bool y
111
Tom Rinia0de0752021-09-22 14:50:29 -0400112config SPL_NAND_LOAD
113 def_bool y
114 depends on NAND_DAVINCI && ARCH_DAVINCI && SPL_NAND_SUPPORT
115
Miquel Raynala430fa02018-08-16 17:30:07 +0200116config NAND_DENALI
117 bool
118 select SYS_NAND_SELF_INIT
119 imply CMD_NAND
120
121config NAND_DENALI_DT
122 bool "Support Denali NAND controller as a DT device"
123 select NAND_DENALI
Masahiro Yamada407b01b2020-01-30 22:07:59 +0900124 depends on OF_CONTROL && DM_MTD
Miquel Raynala430fa02018-08-16 17:30:07 +0200125 help
126 Enable the driver for NAND flash on platforms using a Denali NAND
127 controller as a DT device.
128
Tom Riniccdc7cf2021-09-22 14:50:28 -0400129config NAND_LPC32XX_MLC
130 bool "Support LPC32XX_MLC controller"
131 help
132 Enable the LPC32XX MLC NAND controller.
133
Miquel Raynala430fa02018-08-16 17:30:07 +0200134config NAND_LPC32XX_SLC
135 bool "Support LPC32XX_SLC controller"
136 help
137 Enable the LPC32XX SLC NAND controller.
138
139config NAND_OMAP_GPMC
140 bool "Support OMAP GPMC NAND controller"
141 depends on ARCH_OMAP2PLUS
142 help
143 Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
144 GPMC controller is used for parallel NAND flash devices, and can
145 do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
146 and BCH16 ECC algorithms.
147
148config NAND_OMAP_GPMC_PREFETCH
149 bool "Enable GPMC Prefetch"
150 depends on NAND_OMAP_GPMC
151 default y
152 help
153 On OMAP platforms that use the GPMC controller
154 (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
155 uses the prefetch mode to speed up read operations.
156
157config NAND_OMAP_ELM
158 bool "Enable ELM driver for OMAPxx and AMxx platforms."
159 depends on NAND_OMAP_GPMC && !OMAP34XX
160 help
161 ELM controller is used for ECC error detection (not ECC calculation)
162 of BCH4, BCH8 and BCH16 ECC algorithms.
163 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
164 thus such SoC platforms need to depend on software library for ECC error
165 detection. However ECC calculation on such plaforms would still be
166 done by GPMC controller.
167
168config NAND_VF610_NFC
169 bool "Support for Freescale NFC for VF610"
170 select SYS_NAND_SELF_INIT
Stefan Agnera38c3af2018-12-06 14:57:09 +0100171 select SYS_NAND_DRIVER_ECC_LAYOUT
Miquel Raynala430fa02018-08-16 17:30:07 +0200172 imply CMD_NAND
173 help
174 Enables support for NAND Flash Controller on some Freescale
175 processors like the VF610, MCF54418 or Kinetis K70.
176 The driver supports a maximum 2k page size. The driver
177 currently does not support hardware ECC.
178
Lukasz Majewski8a12d122018-12-03 10:24:50 +0100179if NAND_VF610_NFC
180
181config NAND_VF610_NFC_DT
182 bool "Support Vybrid's vf610 NAND controller as a DT device"
Miquel Raynal1de770d2019-10-03 19:50:04 +0200183 depends on OF_CONTROL && DM_MTD
Lukasz Majewski8a12d122018-12-03 10:24:50 +0100184 help
185 Enable the driver for Vybrid's vf610 NAND flash on platforms
186 using device tree.
187
Miquel Raynala430fa02018-08-16 17:30:07 +0200188choice
189 prompt "Hardware ECC strength"
190 depends on NAND_VF610_NFC
191 default SYS_NAND_VF610_NFC_45_ECC_BYTES
192 help
193 Select the ECC strength used in the hardware BCH ECC block.
194
195config SYS_NAND_VF610_NFC_45_ECC_BYTES
196 bool "24-error correction (45 ECC bytes)"
197
198config SYS_NAND_VF610_NFC_60_ECC_BYTES
199 bool "32-error correction (60 ECC bytes)"
200
201endchoice
202
Lukasz Majewski8a12d122018-12-03 10:24:50 +0100203endif
204
Miquel Raynala430fa02018-08-16 17:30:07 +0200205config NAND_PXA3XX
206 bool "Support for NAND on PXA3xx and Armada 370/XP/38x"
207 select SYS_NAND_SELF_INIT
Shmuel Hazan8dddfff2020-10-29 08:52:18 +0200208 select DM_MTD
Shmuel Hazanaaedaaa2020-10-29 08:52:20 +0200209 select REGMAP
210 select SYSCON
Miquel Raynala430fa02018-08-16 17:30:07 +0200211 imply CMD_NAND
212 help
213 This enables the driver for the NAND flash device found on
214 PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
215
216config NAND_SUNXI
217 bool "Support for NAND on Allwinner SoCs"
218 default ARCH_SUNXI
219 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I
220 select SYS_NAND_SELF_INIT
221 select SYS_NAND_U_BOOT_LOCATIONS
222 select SPL_NAND_SUPPORT
223 imply CMD_NAND
224 ---help---
225 Enable support for NAND. This option enables the standard and
226 SPL drivers.
227 The SPL driver only supports reading from the NAND using DMA
228 transfers.
229
230if NAND_SUNXI
231
232config NAND_SUNXI_SPL_ECC_STRENGTH
233 int "Allwinner NAND SPL ECC Strength"
234 default 64
235
236config NAND_SUNXI_SPL_ECC_SIZE
237 int "Allwinner NAND SPL ECC Step Size"
238 default 1024
239
240config NAND_SUNXI_SPL_USABLE_PAGE_SIZE
241 int "Allwinner NAND SPL Usable Page Size"
242 default 1024
243
244endif
245
246config NAND_ARASAN
247 bool "Configure Arasan Nand"
248 select SYS_NAND_SELF_INIT
Michal Simeka2530922020-08-19 09:59:52 +0200249 depends on DM_MTD
Miquel Raynala430fa02018-08-16 17:30:07 +0200250 imply CMD_NAND
251 help
252 This enables Nand driver support for Arasan nand flash
253 controller. This uses the hardware ECC for read and
254 write operations.
255
256config NAND_MXC
257 bool "MXC NAND support"
258 depends on CPU_ARM926EJS || CPU_ARM1136 || MX5
259 imply CMD_NAND
260 help
261 This enables the NAND driver for the NAND flash controller on the
262 i.MX27 / i.MX31 / i.MX5 rocessors.
263
264config NAND_MXS
265 bool "MXS NAND support"
Peng Fan39320e72020-05-04 22:09:00 +0800266 depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M
Miquel Raynala430fa02018-08-16 17:30:07 +0200267 select SYS_NAND_SELF_INIT
268 imply CMD_NAND
269 select APBH_DMA
Peng Fan39320e72020-05-04 22:09:00 +0800270 select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
271 select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
Miquel Raynala430fa02018-08-16 17:30:07 +0200272 help
273 This enables NAND driver for the NAND flash controller on the
274 MXS processors.
275
276if NAND_MXS
277
278config NAND_MXS_DT
279 bool "Support MXS NAND controller as a DT device"
Miquel Raynal1de770d2019-10-03 19:50:04 +0200280 depends on OF_CONTROL && DM_MTD
Miquel Raynala430fa02018-08-16 17:30:07 +0200281 help
282 Enable the driver for MXS NAND flash on platforms using
283 device tree.
284
285config NAND_MXS_USE_MINIMUM_ECC
286 bool "Use minimum ECC strength supported by the controller"
287 default false
288
289endif
290
291config NAND_ZYNQ
292 bool "Support for Zynq Nand controller"
293 select SYS_NAND_SELF_INIT
Ashok Reddy Soma45397a62019-12-27 04:47:12 -0700294 select DM_MTD
Miquel Raynala430fa02018-08-16 17:30:07 +0200295 imply CMD_NAND
296 help
297 This enables Nand driver support for Nand flash controller
298 found on Zynq SoC.
299
300config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
301 bool "Enable use of 1st stage bootloader timing for NAND"
302 depends on NAND_ZYNQ
303 help
304 This flag prevent U-boot reconfigure NAND flash controller and reuse
305 the NAND timing from 1st stage bootloader.
306
Suneel Garapati05c76062020-08-26 14:37:22 +0200307config NAND_OCTEONTX
308 bool "Support for OcteonTX NAND controller"
309 select SYS_NAND_SELF_INIT
310 imply CMD_NAND
311 help
312 This enables Nand flash controller hardware found on the OcteonTX
313 processors.
314
315config NAND_OCTEONTX_HW_ECC
316 bool "Support Hardware ECC for OcteonTX NAND controller"
317 depends on NAND_OCTEONTX
318 default y
319 help
320 This enables Hardware BCH engine found on the OcteonTX processors to
321 support ECC for NAND flash controller.
322
Christophe Kerello7bb75022019-04-05 11:41:50 +0200323config NAND_STM32_FMC2
324 bool "Support for NAND controller on STM32MP SoCs"
325 depends on ARCH_STM32MP
326 select SYS_NAND_SELF_INIT
327 imply CMD_NAND
328 help
329 Enables support for NAND Flash chips on SoCs containing the FMC2
330 NAND controller. This controller is found on STM32MP SoCs.
331 The controller supports a maximum 8k page size and supports
332 a maximum 8-bit correction error per sector of 512 bytes.
333
Kate Liu161df942020-12-11 13:46:12 -0800334config CORTINA_NAND
335 bool "Support for NAND controller on Cortina-Access SoCs"
336 depends on CORTINA_PLATFORM
337 select SYS_NAND_SELF_INIT
338 select DM_MTD
339 imply CMD_NAND
340 help
341 Enables support for NAND Flash chips on Coartina-Access SoCs platform
342 This controller is found on Presidio/Venus SoCs.
343 The controller supports a maximum 8k page size and supports
344 a maximum 40-bit error correction per sector of 1024 bytes.
345
Yifeng Zhaob12dc5d2021-06-07 16:40:29 +0800346config ROCKCHIP_NAND
347 bool "Support for NAND controller on Rockchip SoCs"
348 depends on ARCH_ROCKCHIP
349 select SYS_NAND_SELF_INIT
350 select DM_MTD
351 imply CMD_NAND
352 help
353 Enables support for NAND Flash chips on Rockchip SoCs platform.
354 This controller is found on Rockchip SoCs.
355 There are four different versions of NAND FLASH Controllers,
356 including:
357 NFC v600: RK2928, RK3066, RK3188
358 NFC v622: RK3036, RK3128
359 NFC v800: RK3308, RV1108
360 NFC v900: PX30, RK3326
361
Miquel Raynala430fa02018-08-16 17:30:07 +0200362comment "Generic NAND options"
363
364config SYS_NAND_BLOCK_SIZE
365 hex "NAND chip eraseblock size"
Tom Rinia0de0752021-09-22 14:50:29 -0400366 depends on ARCH_SUNXI || SPL_NAND_SUPPORT || TPL_NAND_SUPPORT
367 depends on !NAND_MXS_DT && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
Miquel Raynala430fa02018-08-16 17:30:07 +0200368 help
369 Number of data bytes in one eraseblock for the NAND chip on the
370 board. This is the multiple of NAND_PAGE_SIZE and the number of
371 pages.
372
373config SYS_NAND_PAGE_SIZE
374 hex "NAND chip page size"
Tom Rinia0de0752021-09-22 14:50:29 -0400375 depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
376 SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
377 (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
378 depends on !NAND_MXS_DT && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
Miquel Raynala430fa02018-08-16 17:30:07 +0200379 help
380 Number of data bytes in one page for the NAND chip on the
381 board, not including the OOB area.
382
383config SYS_NAND_OOBSIZE
384 hex "NAND chip OOB size"
Tom Rinia0de0752021-09-22 14:50:29 -0400385 depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
386 SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
387 (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
388 depends on !NAND_MXS_DT && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
Miquel Raynala430fa02018-08-16 17:30:07 +0200389 help
390 Number of bytes in the Out-Of-Band area for the NAND chip on
391 the board.
392
393# Enhance depends when converting drivers to Kconfig which use this config
394# option (mxc_nand, ndfc, omap_gpmc).
395config SYS_NAND_BUSWIDTH_16BIT
396 bool "Use 16-bit NAND interface"
397 depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI
398 help
399 Indicates that NAND device has 16-bit wide data-bus. In absence of this
400 config, bus-width of NAND device is assumed to be either 8-bit and later
401 determined by reading ONFI params.
402 Above config is useful when NAND device's bus-width information cannot
403 be determined from on-chip ONFI params, like in following scenarios:
404 - SPL boot does not support reading of ONFI parameters. This is done to
405 keep SPL code foot-print small.
406 - In current U-Boot flow using nand_init(), driver initialization
407 happens in board_nand_init() which is called before any device probe
408 (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are
409 not available while configuring controller. So a static CONFIG_NAND_xx
410 is needed to know the device's bus-width in advance.
411
T Karthik Reddy97fca6a2018-12-03 16:11:58 +0530412config SYS_NAND_MAX_CHIPS
413 int "NAND max chips"
414 default 1
415 depends on NAND_ARASAN
416 help
417 The maximum number of NAND chips per device to be supported.
418
Miquel Raynala430fa02018-08-16 17:30:07 +0200419if SPL
420
421config SYS_NAND_U_BOOT_LOCATIONS
422 bool "Define U-boot binaries locations in NAND"
423 help
424 Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig.
425 This option should not be enabled when compiling U-boot for boards
426 defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h
427 file.
428
429config SYS_NAND_U_BOOT_OFFS
430 hex "Location in NAND to read U-Boot from"
431 default 0x800000 if NAND_SUNXI
432 depends on SYS_NAND_U_BOOT_LOCATIONS
433 help
434 Set the offset from the start of the nand where u-boot should be
435 loaded from.
436
437config SYS_NAND_U_BOOT_OFFS_REDUND
438 hex "Location in NAND to read U-Boot from"
439 default SYS_NAND_U_BOOT_OFFS
440 depends on SYS_NAND_U_BOOT_LOCATIONS
441 help
442 Set the offset from the start of the nand where the redundant u-boot
443 should be loaded from.
444
445config SPL_NAND_AM33XX_BCH
446 bool "Enables SPL-NAND driver which supports ELM based"
447 depends on NAND_OMAP_GPMC && !OMAP34XX
448 default y
449 help
450 Hardware ECC correction. This is useful for platforms which have ELM
451 hardware engine and use NAND boot mode.
452 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
453 so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
454 SPL-NAND driver with software ECC correction support.
455
456config SPL_NAND_DENALI
457 bool "Support Denali NAND controller for SPL"
458 help
459 This is a small implementation of the Denali NAND controller
460 for use on SPL.
461
Masahiro Yamada7a270432020-04-17 16:51:42 +0900462config NAND_DENALI_SPARE_AREA_SKIP_BYTES
463 int "Number of bytes skipped in OOB area"
464 depends on SPL_NAND_DENALI
465 range 0 63
466 help
467 This option specifies the number of bytes to skip from the beginning
468 of OOB area before last ECC sector data starts. This is potentially
469 used to preserve the bad block marker in the OOB area.
470
Miquel Raynala430fa02018-08-16 17:30:07 +0200471config SPL_NAND_SIMPLE
472 bool "Use simple SPL NAND driver"
473 depends on !SPL_NAND_AM33XX_BCH
474 help
475 Support for NAND boot using simple NAND drivers that
476 expose the cmd_ctrl() interface.
477endif
478
479endif # if NAND