blob: c3f10c75a8609ccbfe8055a7a5b6bf1d935c943f [file] [log] [blame]
Stefan Roeseb765ffb2007-06-15 08:18:01 +02001/*
2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21/************************************************************************
22 * lwmon5.h - configuration for lwmon5 board
23 ***********************************************************************/
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27/*-----------------------------------------------------------------------
28 * High Level Configuration Options
29 *----------------------------------------------------------------------*/
30#define CONFIG_LWMON5 1 /* Board is lwmon5 */
31#define CONFIG_440EPX 1 /* Specific PPC440EPx */
Stefan Roesee73846b2007-06-15 11:33:41 +020032#define CONFIG_440 1 /* ... PPC440 family */
Stefan Roeseb765ffb2007-06-15 08:18:01 +020033#define CONFIG_4xx 1 /* ... PPC4xx family */
34#define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */
35
36#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
Stefan Roese3ad63872007-08-21 16:27:57 +020037#define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init */
Stefan Roeseb765ffb2007-06-15 08:18:01 +020038#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
Stefan Roeseb765ffb2007-06-15 08:18:01 +020039
40/*-----------------------------------------------------------------------
41 * Base addresses -- Note these are effective addresses where the
42 * actual resources get mapped (not physical addresses)
43 *----------------------------------------------------------------------*/
44#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
45#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc() */
46
47#define CFG_BOOT_BASE_ADDR 0xf0000000
48#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
Stefan Roese9f24a802007-07-24 09:52:52 +020049#define CFG_FLASH_BASE 0xf8000000 /* start of FLASH */
Stefan Roeseb765ffb2007-06-15 08:18:01 +020050#define CFG_MONITOR_BASE TEXT_BASE
51#define CFG_LIME_BASE_0 0xc0000000
52#define CFG_LIME_BASE_1 0xc1000000
53#define CFG_LIME_BASE_2 0xc2000000
54#define CFG_LIME_BASE_3 0xc3000000
55#define CFG_FPGA_BASE_0 0xc4000000
56#define CFG_FPGA_BASE_1 0xc4200000
57#define CFG_OCM_BASE 0xe0010000 /* ocm */
58#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
59#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
60#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
61#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
62#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
63
64/* Don't change either of these */
65#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
66
67#define CFG_USB2D0_BASE 0xe0000100
68#define CFG_USB_DEVICE 0xe0000000
69#define CFG_USB_HOST 0xe0000400
70
71/*-----------------------------------------------------------------------
72 * Initial RAM & stack pointer
73 *----------------------------------------------------------------------*/
Stefan Roese8f24e062008-01-09 10:28:20 +010074/*
75 * On LWMON5 we use D-cache as init-ram and stack pointer. We also move
76 * the POST_WORD from OCM to a 440EPx register that preserves it's
77 * content during reset (GPT0_COM6). This way we reserve the OCM (16k)
78 * for logbuffer only.
79 */
80#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */
81#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
Stefan Roeseb765ffb2007-06-15 08:18:01 +020082#define CFG_INIT_RAM_END (4 << 10)
Stefan Roese8f24e062008-01-09 10:28:20 +010083#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/
Stefan Roeseb765ffb2007-06-15 08:18:01 +020084#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
Stefan Roese8f24e062008-01-09 10:28:20 +010085#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
86#define CFG_POST_ALT_WORD_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP6)
87 /* unused GPT0 COMP reg */
Stefan Roeseb765ffb2007-06-15 08:18:01 +020088
89/*-----------------------------------------------------------------------
90 * Serial Port
91 *----------------------------------------------------------------------*/
92#undef CFG_EXT_SERIAL_CLOCK /* no external clock provided */
93#define CONFIG_BAUDRATE 115200
94#define CONFIG_SERIAL_MULTI 1
95/* define this if you want console on UART1 */
96#define CONFIG_UART1_CONSOLE 1 /* use UART1 as console */
97
98#define CFG_BAUDRATE_TABLE \
99 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
100
101/*-----------------------------------------------------------------------
102 * Environment
103 *----------------------------------------------------------------------*/
104#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
105
106/*-----------------------------------------------------------------------
107 * FLASH related
108 *----------------------------------------------------------------------*/
109#define CFG_FLASH_CFI /* The flash is CFI compatible */
110#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
111
Stefan Roese9f24a802007-07-24 09:52:52 +0200112#define CFG_FLASH0 0xFC000000
113#define CFG_FLASH1 0xF8000000
114#define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 }
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200115
Stefan Roese9f24a802007-07-24 09:52:52 +0200116#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200117#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
118
119#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
120#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
121
122#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
123#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
124
125#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
126#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
127
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200128#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200129#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
130#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
131
132/* Address and size of Redundant Environment Sector */
133#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
134#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
135
136/*-----------------------------------------------------------------------
137 * DDR SDRAM
138 *----------------------------------------------------------------------*/
139#define CFG_MBYTES_SDRAM (256) /* 256MB */
140#define CFG_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
141#define CONFIG_DDR_DATA_EYE 1 /* use DDR2 optimization */
142#if 0 /* test-only: disable ECC for now */
143#define CONFIG_DDR_ECC 1 /* enable ECC */
Stefan Roese3e4c90c2007-08-10 08:42:55 +0200144#define CFG_POST_ECC_ON CFG_POST_ECC
145#else
146#define CFG_POST_ECC_ON 0
147#endif
Pavel Kolesnikov531e3e82007-07-20 15:03:03 +0200148
149/* POST support */
Stefan Roese75e1a842007-08-24 15:41:42 +0200150#define CONFIG_POST (CFG_POST_CACHE | \
Stefan Roese3e4c90c2007-08-10 08:42:55 +0200151 CFG_POST_CPU | \
Stefan Roese75e1a842007-08-24 15:41:42 +0200152 CFG_POST_ECC_ON | \
Stefan Roese3e4c90c2007-08-10 08:42:55 +0200153 CFG_POST_ETHER | \
Stefan Roese75e1a842007-08-24 15:41:42 +0200154 CFG_POST_FPU | \
155 CFG_POST_I2C | \
156 CFG_POST_MEMORY | \
157 CFG_POST_RTC | \
158 CFG_POST_SPR | \
159 CFG_POST_UART)
Stefan Roese3e4c90c2007-08-10 08:42:55 +0200160
Stefan Roese42d55ea2007-12-22 12:20:09 +0100161#define CFG_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
Stefan Roese3e4c90c2007-08-10 08:42:55 +0200162#define CONFIG_LOGBUFFER
163#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200164
165/*-----------------------------------------------------------------------
166 * I2C
167 *----------------------------------------------------------------------*/
168#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
169#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Stefan Roesec25dd8f2007-08-23 11:02:37 +0200170#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200171#define CFG_I2C_SLAVE 0x7F
172
Stefan Roesec25dd8f2007-08-23 11:02:37 +0200173#define CFG_I2C_EEPROM_ADDR 0x53 /* EEPROM AT24C128 */
174#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
175#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel AT24C128 has */
176 /* 64 byte page write mode using*/
177 /* last 6 bits of the address */
178#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200179#define CFG_EEPROM_PAGE_WRITE_ENABLE
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200180
181#define CONFIG_RTC_PCF8563 1 /* enable Philips PCF8563 RTC */
182#define CFG_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
Stefan Roese3ad63872007-08-21 16:27:57 +0200183#define CFG_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200184
Stefan Roese3ad63872007-08-21 16:27:57 +0200185#define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */
186#if 0
187#define CONFIG_AUTOBOOT_KEYED /* Enable "password" protection */
188#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n"
189#define CONFIG_AUTOBOOT_DELAY_STR " " /* "password" */
190#endif
191
192#define CONFIG_PREBOOT "setenv bootdelay 15"
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200193
194#undef CONFIG_BOOTARGS
195
196#define CONFIG_EXTRA_ENV_SETTINGS \
197 "hostname=lwmon5\0" \
198 "netdev=eth0\0" \
Stefan Roese5d187432007-07-06 11:48:24 +0200199 "unlock=yes\0" \
Stefan Roese3e4c90c2007-08-10 08:42:55 +0200200 "logversion=2\0" \
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200201 "nfsargs=setenv bootargs root=/dev/nfs rw " \
202 "nfsroot=${serverip}:${rootpath}\0" \
203 "ramargs=setenv bootargs root=/dev/ram rw\0" \
204 "addip=setenv bootargs ${bootargs} " \
205 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
206 ":${hostname}:${netdev}:off panic=1\0" \
207 "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
Stefan Roese04625762007-08-29 16:31:18 +0200208 "addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\
209 "flash_nfs=run nfsargs addip addtty addmisc;" \
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200210 "bootm ${kernel_addr}\0" \
Stefan Roese04625762007-08-29 16:31:18 +0200211 "flash_self=run ramargs addip addtty addmisc;" \
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200212 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
Stefan Roese04625762007-08-29 16:31:18 +0200213 "net_nfs=tftp 200000 ${bootfile};" \
214 "run nfsargs addip addtty addmisc;bootm\0" \
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200215 "rootpath=/opt/eldk/ppc_4xxFP\0" \
216 "bootfile=/tftpboot/lwmon5/uImage\0" \
217 "kernel_addr=FC000000\0" \
218 "ramdisk_addr=FC180000\0" \
219 "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
220 "update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \
221 "cp.b 200000 FFF80000 80000\0" \
Detlev Zundeld8ab58b2008-03-06 16:45:53 +0100222 "upd=run load update\0" \
Stefan Roese334043f2007-07-06 12:26:51 +0200223 "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \
224 "autoscr 200000\0" \
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200225 ""
226#define CONFIG_BOOTCOMMAND "run flash_self"
227
228#if 0
229#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
230#else
231#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
232#endif
233
234#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
235#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
236
237#define CONFIG_IBM_EMAC4_V4 1
238#define CONFIG_MII 1 /* MII PHY management */
239#define CONFIG_PHY_ADDR 3 /* PHY address, See schematics */
240
241#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
Stefan Roese3ad63872007-08-21 16:27:57 +0200242#define CONFIG_PHY_RESET_DELAY 300
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200243
244#define CONFIG_HAS_ETH0
245#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
246
247#define CONFIG_NET_MULTI 1
248#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
249#define CONFIG_PHY1_ADDR 1
250
Anatolij Gustschind610a602008-01-11 15:31:09 +0100251/* Video console */
252#define CONFIG_VIDEO
253#define CONFIG_VIDEO_MB862xx
254#define CONFIG_CFB_CONSOLE
255#define CONFIG_VIDEO_LOGO
256#define CONFIG_CONSOLE_EXTRA_INFO
257#define VIDEO_FB_16BPP_PIXEL_SWAP
258
259#define CONFIG_VGA_AS_SINGLE_DEVICE
260#define CONFIG_VIDEO_SW_CURSOR
261#define CONFIG_SPLASH_SCREEN
262
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200263/* USB */
264#ifdef CONFIG_440EPX
265#define CONFIG_USB_OHCI
266#define CONFIG_USB_STORAGE
267
268/* Comment this out to enable USB 1.1 device */
269#define USB_2_0_DEVICE
270
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200271#endif /* CONFIG_440EPX */
272
273/* Partitions */
274#define CONFIG_MAC_PARTITION
275#define CONFIG_DOS_PARTITION
276#define CONFIG_ISO_PARTITION
277
Jon Loeligera22d4da2007-07-08 15:42:59 -0500278/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500279 * BOOTP options
280 */
281#define CONFIG_BOOTP_BOOTFILESIZE
282#define CONFIG_BOOTP_BOOTPATH
283#define CONFIG_BOOTP_GATEWAY
284#define CONFIG_BOOTP_HOSTNAME
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200285
Jon Loeliger079a1362007-07-10 10:12:10 -0500286/*
Jon Loeligera22d4da2007-07-08 15:42:59 -0500287 * Command line configuration.
288 */
289#include <config_cmd_default.h>
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200290
Jon Loeligera22d4da2007-07-08 15:42:59 -0500291#define CONFIG_CMD_ASKENV
292#define CONFIG_CMD_DATE
293#define CONFIG_CMD_DHCP
294#define CONFIG_CMD_DIAG
295#define CONFIG_CMD_EEPROM
296#define CONFIG_CMD_ELF
297#define CONFIG_CMD_FAT
298#define CONFIG_CMD_I2C
299#define CONFIG_CMD_IRQ
Stefan Roese3b3bff42007-08-14 16:36:29 +0200300#define CONFIG_CMD_LOG
Jon Loeligera22d4da2007-07-08 15:42:59 -0500301#define CONFIG_CMD_MII
302#define CONFIG_CMD_NET
303#define CONFIG_CMD_NFS
304#define CONFIG_CMD_PCI
305#define CONFIG_CMD_PING
306#define CONFIG_CMD_REGINFO
307#define CONFIG_CMD_SDRAM
308
Anatolij Gustschind610a602008-01-11 15:31:09 +0100309#ifdef CONFIG_VIDEO
310#define CONFIG_CMD_BMP
311#endif
312
Jon Loeligera22d4da2007-07-08 15:42:59 -0500313#ifdef CONFIG_440EPX
314#define CONFIG_CMD_USB
315#endif
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200316
317/*-----------------------------------------------------------------------
318 * Miscellaneous configurable options
319 *----------------------------------------------------------------------*/
Jon Loeligera22d4da2007-07-08 15:42:59 -0500320#define CONFIG_SUPPORT_VFAT
321
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200322#define CFG_LONGHELP /* undef to save memory */
323#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Wolfgang Denk58d20422008-01-16 00:01:01 +0100324
325#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
326#ifdef CFG_HUSH_PARSER
327#define CFG_PROMPT_HUSH_PS2 "> "
328#endif
329
Jon Loeligera22d4da2007-07-08 15:42:59 -0500330#if defined(CONFIG_CMD_KGDB)
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200331#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
332#else
333#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
334#endif
335#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
336#define CFG_MAXARGS 16 /* max number of command args */
337#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
338
339#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
340#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
341
342#define CFG_LOAD_ADDR 0x100000 /* default load address */
343#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
344
345#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
346
347#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
348#define CONFIG_LOOPW 1 /* enable loopw command */
349#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
350#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
351#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
352
353/*-----------------------------------------------------------------------
354 * PCI stuff
355 *----------------------------------------------------------------------*/
356/* General PCI */
357#define CONFIG_PCI /* include pci support */
358#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
359#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
360#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
361
362/* Board-specific PCI */
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200363#define CFG_PCI_TARGET_INIT
364#define CFG_PCI_MASTER_INIT
365
366#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
367#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
368
Stefan Roese87c18332007-10-02 11:44:19 +0200369/*
370 * ToDo: Watchdog is not test fully, so exclude it for now
371 */
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200372#define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */
Yuri Tikhonov2e721092008-02-21 14:23:42 +0100373#define CONFIG_WD_PERIOD 40000 /* in usec */
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200374
375/*
376 * For booting Linux, the board info and command line data
377 * have to be in the first 8 MB of memory, since this is
378 * the maximum mapped by the Linux kernel during initialization.
379 */
380#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
381
382/*-----------------------------------------------------------------------
383 * External Bus Controller (EBC) Setup
384 *----------------------------------------------------------------------*/
385#define CFG_FLASH CFG_FLASH_BASE
386
387/* Memory Bank 0 (NOR-FLASH) initialization */
388#define CFG_EBC_PB0AP 0x03050200
Stefan Roese9f24a802007-07-24 09:52:52 +0200389#define CFG_EBC_PB0CR (CFG_FLASH | 0xfc000)
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200390
391/* Memory Bank 1 (Lime) initialization */
392#define CFG_EBC_PB1AP 0x01004380
393#define CFG_EBC_PB1CR (CFG_LIME_BASE_0 | 0xdc000)
394
395/* Memory Bank 2 (FPGA) initialization */
396#define CFG_EBC_PB2AP 0x01004400
397#define CFG_EBC_PB2CR (CFG_FPGA_BASE_0 | 0x1c000)
398
399/* Memory Bank 3 (FPGA2) initialization */
400#define CFG_EBC_PB3AP 0x01004400
401#define CFG_EBC_PB3CR (CFG_FPGA_BASE_1 | 0x1c000)
402
403#define CFG_EBC_CFG 0xb8400000
404
405/*-----------------------------------------------------------------------
Stefan Roese04e6c382007-07-04 10:06:30 +0200406 * Graphics (Fujitsu Lime)
407 *----------------------------------------------------------------------*/
408/* SDRAM Clock frequency adjustment register */
Anatolij Gustschinb66091d2007-07-26 15:08:01 +0200409#define CFG_LIME_SDRAM_CLOCK 0xC1FC0038
410/* Lime Clock frequency is to set 100MHz */
411#define CFG_LIME_CLOCK_100MHZ 0x00000
412#if 0
413/* Lime Clock frequency for 133MHz */
Stefan Roese04e6c382007-07-04 10:06:30 +0200414#define CFG_LIME_CLOCK_133MHZ 0x10000
Anatolij Gustschinb66091d2007-07-26 15:08:01 +0200415#endif
Stefan Roese04e6c382007-07-04 10:06:30 +0200416
417/* SDRAM Parameter register */
418#define CFG_LIME_MMR 0xC1FCFFFC
Anatolij Gustschinb66091d2007-07-26 15:08:01 +0200419/* SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
420 and pixel flare on display when 133MHz was configured. According to
421 SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed Grade */
422#ifdef CFG_LIME_CLOCK_133MHZ
423#define CFG_LIME_MMR_VALUE 0x414FB7F3
424#else
Stefan Roese04e6c382007-07-04 10:06:30 +0200425#define CFG_LIME_MMR_VALUE 0x414FB7F2
Anatolij Gustschinb66091d2007-07-26 15:08:01 +0200426#endif
Stefan Roese04e6c382007-07-04 10:06:30 +0200427
428/*-----------------------------------------------------------------------
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200429 * GPIO Setup
430 *----------------------------------------------------------------------*/
431#define CFG_GPIO_PHY1_RST 12
432#define CFG_GPIO_FLASH_WP 14
433#define CFG_GPIO_PHY0_RST 22
Stefan Roesec25dd8f2007-08-23 11:02:37 +0200434#define CFG_GPIO_EEPROM_EXT_WP 55
435#define CFG_GPIO_EEPROM_INT_WP 57
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200436#define CFG_GPIO_LIME_S 59
437#define CFG_GPIO_LIME_RST 60
Stefan Roesed7bfa622007-08-24 15:19:10 +0200438#define CFG_GPIO_WATCHDOG 63
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200439
440/*-----------------------------------------------------------------------
441 * PPC440 GPIO Configuration
442 */
Stefan Roeseaee747f2007-11-15 14:23:55 +0100443#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200444{ \
445/* GPIO Core 0 */ \
446{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
447{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
448{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
449{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
450{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
451{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
452{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
453{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
454{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
455{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
456{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
457{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
458{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
459{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
460{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
Stefan Roese20d500d2007-10-23 10:17:42 +0200461{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15 */ \
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200462{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200463{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \
464{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \
465{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7) */ \
466{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
467{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
468{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
469{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
470{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2) */ \
471{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3) */ \
472{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
473{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
474{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \
475{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
476{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
477{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
478}, \
479{ \
480/* GPIO Core 1 */ \
481{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
482{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
483{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
484{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
485{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \
486{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
487{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
488{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
489{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
490{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
491{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
492{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
493{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
494{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
495{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
496{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
497{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
498{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO49 Unselect via TraceSelect Bit */ \
Stefan Roese04e6c382007-07-04 10:06:30 +0200499{GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200500{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
501{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
Stefan Roese20d500d2007-10-23 10:17:42 +0200502{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200503{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
504{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \
505{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
506{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57 Unselect via TraceSelect Bit */ \
Stefan Roese3e954be2007-09-11 14:12:55 +0200507{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200508{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
509{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
510{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
511{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
512{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
513} \
514}
515
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200516/*
517 * Internal Definitions
518 *
519 * Boot Flags
520 */
521#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
522#define BOOTFLAG_WARM 0x02 /* Software reboot */
523
Jon Loeligera22d4da2007-07-08 15:42:59 -0500524#if defined(CONFIG_CMD_KGDB)
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200525#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
526#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
527#endif
528#endif /* __CONFIG_H */