| Sandeep Sheriker Mallikarjun | 5142266 | 2019-09-27 13:08:52 +0000 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Configuation settings for the SAM9X60EK board. |
| 4 | * |
| 5 | * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries |
| 6 | * |
| 7 | * Author: Sandeep Sheriker M <sandeep.sheriker@microchip.com> |
| 8 | */ |
| 9 | |
| 10 | #ifndef __CONFIG_H__ |
| 11 | #define __CONFIG_H__ |
| 12 | |
| 13 | /* ARM asynchronous clock */ |
| 14 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 |
| 15 | #define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */ |
| 16 | |
| 17 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
| 18 | #define CONFIG_SETUP_MEMORY_TAGS |
| 19 | #define CONFIG_INITRD_TAG |
| 20 | #define CONFIG_SKIP_LOWLEVEL_INIT |
| 21 | |
| 22 | #define CONFIG_USART_BASE ATMEL_BASE_DBGU |
| 23 | #define CONFIG_USART_ID 0 /* ignored in arm */ |
| 24 | |
| 25 | /* general purpose I/O */ |
| 26 | #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ |
| 27 | |
| 28 | /* |
| 29 | * BOOTP options |
| 30 | */ |
| 31 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 32 | |
| 33 | /* |
| 34 | * define CONFIG_USB_EHCI_HCD to enable USB Hi-Speed (aka 2.0) |
| 35 | * NB: in this case, USB 1.1 devices won't be recognized. |
| 36 | */ |
| 37 | |
| 38 | /* SDRAM */ |
| 39 | #define CONFIG_SYS_SDRAM_BASE 0x20000000 |
| 40 | #define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 megs */ |
| 41 | |
| 42 | #define CONFIG_SYS_INIT_SP_ADDR \ |
| 43 | (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) |
| 44 | |
| Tudor Ambarus | 8ed15e4 | 2019-09-27 13:09:07 +0000 | [diff] [blame] | 45 | /* NAND flash */ |
| 46 | #ifdef CONFIG_CMD_NAND |
| 47 | #define CONFIG_NAND_ATMEL |
| 48 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 49 | #define CONFIG_SYS_NAND_BASE 0x40000000 |
| 50 | #define CONFIG_SYS_NAND_MASK_ALE BIT(21) |
| 51 | #define CONFIG_SYS_NAND_MASK_CLE BIT(22) |
| 52 | #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 |
| 53 | #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 |
| 54 | #define CONFIG_SYS_NAND_ONFI_DETECTION |
| Tudor Ambarus | 8ed15e4 | 2019-09-27 13:09:07 +0000 | [diff] [blame] | 55 | #endif |
| 56 | |
| 57 | /* PMECC & PMERRLOC */ |
| 58 | #define CONFIG_ATMEL_NAND_HWECC |
| 59 | #define CONFIG_ATMEL_NAND_HW_PMECC |
| 60 | #define CONFIG_PMECC_CAP 8 |
| 61 | #define CONFIG_PMECC_SECTOR_SIZE 512 |
| 62 | |
| Sandeep Sheriker Mallikarjun | 5142266 | 2019-09-27 13:08:52 +0000 | [diff] [blame] | 63 | #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ |
| 64 | |
| 65 | #ifdef CONFIG_SD_BOOT |
| 66 | /* bootstrap + u-boot + env + linux in sd card */ |
| 67 | #define CONFIG_BOOTCOMMAND \ |
| 68 | "fatload mmc 0:1 0x21000000 at91-sam9x60ek.dtb;" \ |
| 69 | "fatload mmc 0:1 0x22000000 zImage;" \ |
| 70 | "bootz 0x22000000 - 0x21000000" |
| Tudor Ambarus | 8ed15e4 | 2019-09-27 13:09:07 +0000 | [diff] [blame] | 71 | |
| 72 | #elif defined(CONFIG_NAND_BOOT) |
| 73 | /* bootstrap + u-boot + env + linux in nandflash */ |
| Tudor Ambarus | 8ed15e4 | 2019-09-27 13:09:07 +0000 | [diff] [blame] | 74 | #define CONFIG_BOOTCOMMAND "nand read " \ |
| 75 | "0x22000000 0x200000 0x600000; " \ |
| 76 | "nand read 0x21000000 0x180000 0x20000; " \ |
| 77 | "bootz 0x22000000 - 0x21000000" |
| Tudor Ambarus | 8c04ea7 | 2019-09-27 13:09:15 +0000 | [diff] [blame] | 78 | |
| 79 | #elif defined(CONFIG_QSPI_BOOT) |
| 80 | /* bootstrap + u-boot + env + linux in SPI NOR flash */ |
| 81 | #define CONFIG_BOOTCOMMAND "sf probe 0; " \ |
| 82 | "sf read 0x21000000 0x180000 0x80000; " \ |
| 83 | "sf read 0x22000000 0x200000 0x600000; " \ |
| 84 | "bootz 0x22000000 - 0x21000000" |
| Sandeep Sheriker Mallikarjun | 5142266 | 2019-09-27 13:08:52 +0000 | [diff] [blame] | 85 | #endif |
| 86 | |
| 87 | /* |
| 88 | * Size of malloc() pool |
| 89 | */ |
| 90 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000) |
| 91 | |
| 92 | #endif |