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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Christophe Kerello4e280b92017-09-13 18:00:08 +02002/*
Patrice Chotard3bc599c2017-10-23 09:53:58 +02003 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
Patrice Chotard0f8106f2020-12-02 18:47:30 +01004 * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
Christophe Kerello4e280b92017-09-13 18:00:08 +02005 */
6
Patrick Delaunay8e80ba52020-11-06 19:01:43 +01007#define LOG_CATEGORY UCLASS_NOP
8
Christophe Kerello4e280b92017-09-13 18:00:08 +02009#include <common.h>
10#include <dm.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060011#include <log.h>
Christophe Kerello4e280b92017-09-13 18:00:08 +020012#include <misc.h>
Patrice Chotard928954f2017-11-15 13:14:51 +010013#include <stm32_rcc.h>
14#include <dm/device-internal.h>
Simon Glass336d4612020-02-03 07:36:16 -070015#include <dm/device_compat.h>
Christophe Kerello4e280b92017-09-13 18:00:08 +020016#include <dm/lists.h>
17
Patrice Chotard8b414642018-04-11 17:07:45 +020018struct stm32_rcc_clk stm32_rcc_clk_f42x = {
Patrice Chotard928954f2017-11-15 13:14:51 +010019 .drv_name = "stm32fx_rcc_clock",
Patrice Chotard8b414642018-04-11 17:07:45 +020020 .soc = STM32F42X,
21};
22
23struct stm32_rcc_clk stm32_rcc_clk_f469 = {
24 .drv_name = "stm32fx_rcc_clock",
25 .soc = STM32F469,
Patrice Chotard928954f2017-11-15 13:14:51 +010026};
27
28struct stm32_rcc_clk stm32_rcc_clk_f7 = {
29 .drv_name = "stm32fx_rcc_clock",
30 .soc = STM32F7,
31};
32
33struct stm32_rcc_clk stm32_rcc_clk_h7 = {
34 .drv_name = "stm32h7_rcc_clock",
35};
36
Patrick Delaunayd090cba2018-07-09 15:17:20 +020037struct stm32_rcc_clk stm32_rcc_clk_mp1 = {
38 .drv_name = "stm32mp1_clk",
39 .soc = STM32MP1,
40};
41
Christophe Kerello4e280b92017-09-13 18:00:08 +020042static int stm32_rcc_bind(struct udevice *dev)
43{
Christophe Kerello4e280b92017-09-13 18:00:08 +020044 struct udevice *child;
Patrice Chotard928954f2017-11-15 13:14:51 +010045 struct driver *drv;
46 struct stm32_rcc_clk *rcc_clk =
47 (struct stm32_rcc_clk *)dev_get_driver_data(dev);
48 int ret;
Christophe Kerello4e280b92017-09-13 18:00:08 +020049
Patrick Delaunay8e80ba52020-11-06 19:01:43 +010050 dev_dbg(dev, "RCC bind\n");
Patrice Chotard928954f2017-11-15 13:14:51 +010051 drv = lists_driver_lookup_name(rcc_clk->drv_name);
52 if (!drv) {
Patrick Delaunay8e80ba52020-11-06 19:01:43 +010053 dev_err(dev, "Cannot find driver '%s'\n", rcc_clk->drv_name);
Patrice Chotard928954f2017-11-15 13:14:51 +010054 return -ENOENT;
55 }
56
57 ret = device_bind_with_driver_data(dev, drv, rcc_clk->drv_name,
58 rcc_clk->soc,
59 dev_ofnode(dev), &child);
60
Christophe Kerello4e280b92017-09-13 18:00:08 +020061 if (ret)
62 return ret;
63
Patrick Delaunayd090cba2018-07-09 15:17:20 +020064 drv = lists_driver_lookup_name("stm32_rcc_reset");
65 if (!drv) {
66 dev_err(dev, "Cannot find driver stm32_rcc_reset'\n");
67 return -ENOENT;
68 }
69
70 return device_bind_with_driver_data(dev, drv, "stm32_rcc_reset",
71 rcc_clk->soc,
72 dev_ofnode(dev), &child);
Christophe Kerello4e280b92017-09-13 18:00:08 +020073}
74
Christophe Kerello4e280b92017-09-13 18:00:08 +020075
76static const struct udevice_id stm32_rcc_ids[] = {
Patrice Chotard8b414642018-04-11 17:07:45 +020077 {.compatible = "st,stm32f42xx-rcc", .data = (ulong)&stm32_rcc_clk_f42x },
78 {.compatible = "st,stm32f469-rcc", .data = (ulong)&stm32_rcc_clk_f469 },
Patrice Chotard928954f2017-11-15 13:14:51 +010079 {.compatible = "st,stm32f746-rcc", .data = (ulong)&stm32_rcc_clk_f7 },
80 {.compatible = "st,stm32h743-rcc", .data = (ulong)&stm32_rcc_clk_h7 },
Patrick Delaunayd090cba2018-07-09 15:17:20 +020081 {.compatible = "st,stm32mp1-rcc", .data = (ulong)&stm32_rcc_clk_mp1 },
Christophe Kerello4e280b92017-09-13 18:00:08 +020082 { }
83};
84
85U_BOOT_DRIVER(stm32_rcc) = {
86 .name = "stm32-rcc",
Patrick Delaunay13234702019-08-02 13:08:08 +020087 .id = UCLASS_NOP,
Christophe Kerello4e280b92017-09-13 18:00:08 +020088 .of_match = stm32_rcc_ids,
89 .bind = stm32_rcc_bind,
Christophe Kerello4e280b92017-09-13 18:00:08 +020090};