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wdenkc15f3122004-10-10 22:44:24 +00001/*
2 * (C) Copyright 2002,2003 Motorola,Inc.
3 * Xianghua Xiao <X.Xiao@motorola.com>
4 *
5 * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
6 * Added support for Wind River SBC8560 board
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27/* mpc8560ads board configuration file */
28/* please refer to doc/README.mpc85xx for more info */
29/* make sure you change the MAC address and other network params first,
30 * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
31 */
wdenk8b74bf32004-10-11 23:10:30 +000032
wdenkc15f3122004-10-10 22:44:24 +000033#ifndef __CONFIG_H
34#define __CONFIG_H
35
36#if XXX
37#define DEBUG /* General debug */
38#define ET_DEBUG
39#endif
40#define TSEC_DEBUG
41
42/* High Level Configuration Options */
43#define CONFIG_BOOKE 1 /* BOOKE */
44#define CONFIG_E500 1 /* BOOKE e500 family */
45#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
46#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */
47
48
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050049#define CONFIG_CPM2 1 /* has CPM2 */
wdenkc15f3122004-10-10 22:44:24 +000050#define CONFIG_SBC8560 1 /* configuration for SBC8560 board */
51
52#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific (supplement) */
53
54#define CONFIG_TSEC_ENET /* tsec ethernet support */
55#undef CONFIG_PCI /* pci ethernet support */
56#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
57
58
59#define CONFIG_ENV_OVERWRITE
60
61/* Using Localbus SDRAM to emulate flash before we can program the flash,
62 * normally you need a flash-boot image(u-boot.bin), if so undef this.
63 */
64#undef CONFIG_RAM_AS_FLASH
65
66#if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */
67 #define CONFIG_SYS_CLK_FREQ 66000000/* sysclk for MPC85xx */
68#else
69 #define CONFIG_SYS_CLK_FREQ 33000000/* most pci cards are 33Mhz */
70#endif
71
72/* below can be toggled for performance analysis. otherwise use default */
73#define CONFIG_L2_CACHE /* toggle L2 cache */
74#undef CONFIG_BTB /* toggle branch predition */
75#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */
76
77#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
78
79#undef CFG_DRAM_TEST /* memory test, takes time */
80#define CFG_MEMTEST_START 0x00200000 /* memtest region */
81#define CFG_MEMTEST_END 0x00400000
82
83#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
84 defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
85 defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
86#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
87#endif
88
89/*
90 * Base addresses -- Note these are effective addresses where the
91 * actual resources get mapped (not physical addresses)
92 */
93#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
94
95#if XXX
96 #define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */
97#else
98 #define CFG_CCSRBAR 0xff700000 /* default CCSRBAR */
99#endif
100#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
101
102#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
103#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
104#define CFG_SDRAM_SIZE 512 /* DDR is 512MB */
105#define SPD_EEPROM_ADDRESS 0x55 /* DDR DIMM */
106
107#undef CONFIG_DDR_ECC /* only for ECC DDR module */
108#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
109
110#if defined(CONFIG_MPC85xx_REV1)
111 #define CONFIG_DDR_DLL /* possible DLL fix needed */
112#endif
113
114#undef CONFIG_CLOCKS_IN_MHZ
115
116#if defined(CONFIG_RAM_AS_FLASH)
117 #define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
118 #define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 8M */
119 #define CFG_BR0_PRELIM 0xf8000801 /* port size 8bit */
120 #define CFG_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */
121#else /* Boot from real Flash */
122 #define CFG_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */
123 #define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */
124 #define CFG_BR0_PRELIM 0xff800801 /* port size 8bit */
125 #define CFG_OR0_PRELIM 0xff800ff7 /* 8MB Flash */
126#endif
127#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
128
129/* local bus definitions */
130#define CFG_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */
131#define CFG_OR1_PRELIM 0xfc000ff7
132
133#define CFG_BR2_PRELIM 0x00000000 /* CS2 not used */
134#define CFG_OR2_PRELIM 0x00000000
135
136#define CFG_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */
137#define CFG_OR3_PRELIM 0xfc000cc1
138
139#if defined(CONFIG_RAM_AS_FLASH)
140 #define CFG_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */
141#else
142 #define CFG_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */
143#endif
144#define CFG_OR4_PRELIM 0xfc000cc1
145
146#define CFG_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */
147#if 1
148 #define CFG_OR5_PRELIM 0xff000ff7
149#else
150 #define CFG_OR5_PRELIM 0xff0000f0
151#endif
152
153#define CFG_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */
154#define CFG_OR6_PRELIM 0xfc000ff7
155#define CFG_LBC_LCRR 0x00030002 /* local bus freq */
156#define CFG_LBC_LBCR 0x00000000
157#define CFG_LBC_LSRT 0x20000000
158#define CFG_LBC_MRTPR 0x20000000
159#define CFG_LBC_LSDMR_1 0x2861b723
160#define CFG_LBC_LSDMR_2 0x0861b723
161#define CFG_LBC_LSDMR_3 0x0861b723
162#define CFG_LBC_LSDMR_4 0x1861b723
163#define CFG_LBC_LSDMR_5 0x4061b723
164
165/* just hijack the MOT BCSR def for SBC8560 misc devices */
166#define CFG_BCSR ((CFG_BR5_PRELIM & 0xff000000)|0x00400000)
167/* the size of CS5 needs to be >= 16M for TLB and LAW setups */
168
169#define CONFIG_L1_INIT_RAM
170#define CFG_INIT_RAM_LOCK 1
171#define CFG_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */
172#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
173
174#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
175#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
176#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
177
178#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
179#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
180
181/* Serial Port */
182#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
183#undef CONFIG_CONS_NONE /* define if console on something else */
184
185#define CONFIG_CONS_INDEX 1
186#undef CONFIG_SERIAL_SOFTWARE_FIFO
187#define CFG_NS16550
188#define CFG_NS16550_SERIAL
189#define CFG_NS16550_REG_SIZE 1
190#define CFG_NS16550_CLK 1843200 /* get_bus_freq(0) */
191#define CONFIG_BAUDRATE 9600
192
193#define CFG_BAUDRATE_TABLE \
194 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
195
196#define CFG_NS16550_COM1 ((CFG_BR5_PRELIM & 0xff000000)+0x00700000)
197#define CFG_NS16550_COM2 ((CFG_BR5_PRELIM & 0xff000000)+0x00800000)
198
199/* Use the HUSH parser */
200#define CFG_HUSH_PARSER
201#ifdef CFG_HUSH_PARSER
202#define CFG_PROMPT_HUSH_PS2 "> "
203#endif
204
205/* I2C */
206#define CONFIG_HARD_I2C /* I2C with hardware support*/
207#undef CONFIG_SOFT_I2C /* I2C bit-banged */
208#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
209#define CFG_I2C_SLAVE 0x7F
210#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
211
212#define CFG_PCI_MEM_BASE 0xC0000000
213#define CFG_PCI_MEM_PHYS 0xC0000000
214#define CFG_PCI_MEM_SIZE 0x10000000
215
216#if defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */
217
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500218# define CONFIG_NET_MULTI 1
219# define CONFIG_MII 1 /* MII PHY management */
220# define CONFIG_MPC85xx_TSEC1
221# define CONFIG_MPC85xx_TSEC1_NAME "TSEC0"
222# define TSEC1_PHY_ADDR 25
223# define TSEC1_PHYIDX 0
224/* Options are: TSEC0 */
225# define CONFIG_ETHPRIME "TSEC0"
wdenkc15f3122004-10-10 22:44:24 +0000226
wdenk8b74bf32004-10-11 23:10:30 +0000227
wdenkc15f3122004-10-10 22:44:24 +0000228#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
229
230 #undef CONFIG_ETHER_NONE /* define if ether on something else */
231 #define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */
232 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */
wdenk8b74bf32004-10-11 23:10:30 +0000233
wdenkc15f3122004-10-10 22:44:24 +0000234 #if (CONFIG_ETHER_INDEX == 2)
235 /*
236 * - Rx-CLK is CLK13
237 * - Tx-CLK is CLK14
238 * - Select bus for bd/buffers
239 * - Full duplex
240 */
241 #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
242 #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
243 #define CFG_CPMFCR_RAMTYPE 0
244 #define CFG_FCC_PSMR (FCC_PSMR_FDE)
wdenk8b74bf32004-10-11 23:10:30 +0000245
wdenkc15f3122004-10-10 22:44:24 +0000246 #elif (CONFIG_ETHER_INDEX == 3)
247 /* need more definitions here for FE3 */
248 #endif /* CONFIG_ETHER_INDEX */
wdenk8b74bf32004-10-11 23:10:30 +0000249
wdenkc15f3122004-10-10 22:44:24 +0000250 #define CONFIG_MII /* MII PHY management */
251 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
252 /*
253 * GPIO pins used for bit-banged MII communications
254 */
255 #define MDIO_PORT 2 /* Port C */
256 #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
257 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
258 #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
259
260 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
261 else iop->pdat &= ~0x00400000
262
263 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
264 else iop->pdat &= ~0x00200000
265
266 #define MIIDELAY udelay(1)
wdenk8b74bf32004-10-11 23:10:30 +0000267
wdenkc15f3122004-10-10 22:44:24 +0000268#endif
269
270/*-----------------------------------------------------------------------
271 * FLASH and environment organization
272 */
273
274#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
275#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
276#if 0
277#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
278#define CFG_FLASH_PROTECTION /* use hardware protection */
279#endif
280#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
281#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
282
283#undef CFG_FLASH_CHECKSUM
284#define CFG_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */
285#define CFG_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */
286
287#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
288
289#if 0
290/* XXX This doesn't work and I don't want to fix it */
291#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
292 #define CFG_RAMBOOT
293#else
294 #undef CFG_RAMBOOT
295#endif
296#endif
297
298/* Environment */
299#if !defined(CFG_RAMBOOT)
300 #if defined(CONFIG_RAM_AS_FLASH)
301 #define CFG_ENV_IS_NOWHERE
302 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000)
303 #define CFG_ENV_SIZE 0x2000
304 #else
305 #define CFG_ENV_IS_IN_FLASH 1
306 #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
307 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
308 #define CFG_ENV_SIZE 0x2000 /* CFG_ENV_SECT_SIZE */
309 #endif
310#else
311 #define CFG_NO_FLASH 1 /* Flash is not usable now */
312 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
313 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
314 #define CFG_ENV_SIZE 0x2000
315#endif
316
317#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600"
318/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/
319#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000"
320#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */
321
322#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
323#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
324
325#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
326 #if defined(CONFIG_PCI)
327 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \
328 CFG_CMD_PING | CFG_CMD_I2C) & \
329 ~(CFG_CMD_ENV | \
330 CFG_CMD_LOADS ))
331 #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC))
332 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \
333 CFG_CMD_PING | CFG_CMD_I2C) & \
334 ~(CFG_CMD_ENV))
335 #endif
336#else
337 #if defined(CONFIG_PCI)
338 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \
339 CFG_CMD_PING | CFG_CMD_I2C)
340 #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC))
341 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \
342 CFG_CMD_PING | CFG_CMD_I2C)
343 #endif
344#endif
345
346#include <cmd_confdefs.h>
347
348#undef CONFIG_WATCHDOG /* watchdog disabled */
349
350/*
351 * Miscellaneous configurable options
352 */
353#define CFG_LONGHELP /* undef to save memory */
354#define CFG_PROMPT "SBC8560=> " /* Monitor Command Prompt */
355#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
356 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
357#else
358 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
359#endif
360#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
361#define CFG_MAXARGS 16 /* max number of command args */
362#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
363#define CFG_LOAD_ADDR 0x1000000 /* default load address */
364#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
365
366/*
367 * For booting Linux, the board info and command line data
368 * have to be in the first 8 MB of memory, since this is
369 * the maximum mapped by the Linux kernel during initialization.
370 */
371#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
372
373/* Cache Configuration */
374#define CFG_DCACHE_SIZE 32768
375#define CFG_CACHELINE_SIZE 32
376#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
377 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
378#endif
379
380/*
381 * Internal Definitions
382 *
383 * Boot Flags
384 */
385#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
386#define BOOTFLAG_WARM 0x02 /* Software reboot */
387
388#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
389 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
390 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
391#endif
392
393/*Note: change below for your network setting!!! */
394#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
wdenke2ffd592004-12-31 09:32:47 +0000395# define CONFIG_ETHADDR 00:vv:ww:xx:yy:8a
396# define CONFIG_HAS_ETH1
397# define CONFIG_ETH1ADDR 00:vv:ww:xx:yy:8b
398# define CONFIG_HAS_ETH2
399# define CONFIG_ETH2ADDR 00:vv:ww:xx:yy:8c
wdenkc15f3122004-10-10 22:44:24 +0000400#endif
401
402#define CONFIG_SERVERIP YourServerIP
403#define CONFIG_IPADDR YourTargetIP
404#define CONFIG_GATEWAYIP YourGatewayIP
405#define CONFIG_NETMASK 255.255.255.0
406#define CONFIG_HOSTNAME SBC8560
407#define CONFIG_ROOTPATH YourRootPath
408#define CONFIG_BOOTFILE YourImageName
409
410#endif /* __CONFIG_H */