| wdenk | e85390d | 2002-04-01 14:29:03 +0000 | [diff] [blame] | 1 | #ifndef _405GP_PCI_H |
| 2 | #define _405GP_PCI_H |
| 3 | |
| 4 | /*----------------------------------------------------------------------------+ |
| 5 | | 405GP PCI core memory map defines. |
| 6 | +----------------------------------------------------------------------------*/ |
| 7 | #define MIN_PCI_MEMADDR1 0x80000000 |
| 8 | #define MIN_PCI_MEMADDR2 0x00000000 |
| 9 | #define MIN_PLB_PCI_IOADDR 0xE8000000 /* PLB side of PCI I/O address space */ |
| 10 | #define MIN_PCI_PCI_IOADDR 0x00000000 /* PCI side of PCI I/O address space */ |
| 11 | #define MAX_PCI_DEVICES 32 |
| 12 | |
| 13 | /*----------------------------------------------------------------------------+ |
| 14 | | Defines for the 405GP PCI Config address and data registers followed by |
| 15 | | defines for the standard PCI device configuration header. |
| 16 | +----------------------------------------------------------------------------*/ |
| 17 | #define PCICFGADR 0xEEC00000 |
| 18 | #define PCICFGDATA 0xEEC00004 |
| 19 | |
| 20 | #define PCIBUSNUM 0x40 /* 405GP specific parameters */ |
| 21 | #define PCISUBBUSNUM 0x41 |
| 22 | #define PCIDISCOUNT 0x42 |
| 23 | #define PCIBRDGOPT1 0x4A |
| 24 | #define PCIBRDGOPT2 0x60 |
| 25 | |
| 26 | /*----------------------------------------------------------------------------+ |
| 27 | | Defines for 405GP PCI Master local configuration regs. |
| 28 | +----------------------------------------------------------------------------*/ |
| 29 | #define PMM0LA 0xEF400000 |
| 30 | #define PMM0MA 0xEF400004 |
| 31 | #define PMM0PCILA 0xEF400008 |
| 32 | #define PMM0PCIHA 0xEF40000C |
| 33 | #define PMM1LA 0xEF400010 |
| 34 | #define PMM1MA 0xEF400014 |
| 35 | #define PMM1PCILA 0xEF400018 |
| 36 | #define PMM1PCIHA 0xEF40001C |
| 37 | #define PMM2LA 0xEF400020 |
| 38 | #define PMM2MA 0xEF400024 |
| 39 | #define PMM2PCILA 0xEF400028 |
| 40 | #define PMM2PCIHA 0xEF40002C |
| 41 | |
| 42 | /*----------------------------------------------------------------------------+ |
| 43 | | Defines for 405GP PCI Target local configuration regs. |
| 44 | +----------------------------------------------------------------------------*/ |
| 45 | #define PTM1MS 0xEF400030 |
| 46 | #define PTM1LA 0xEF400034 |
| 47 | #define PTM2MS 0xEF400038 |
| 48 | #define PTM2LA 0xEF40003C |
| 49 | |
| 50 | #define PCIDEVID_405GP 0x0 |
| 51 | |
| 52 | #endif |