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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Stefan Roese19fc2ea2014-10-22 12:13:14 +02002/*
3 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
4 *
5 * U-Boot version:
Stefan Roesee3b9c982015-11-19 07:46:15 +01006 * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
Stefan Roese19fc2ea2014-10-22 12:13:14 +02007 *
8 * Based on the Linux version which is:
9 * Copyright (C) 2012 Marvell
10 *
11 * Rami Rosen <rosenr@marvell.com>
12 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Stefan Roese19fc2ea2014-10-22 12:13:14 +020013 */
14
15#include <common.h>
Simon Glass1eb69ae2019-11-14 12:57:39 -070016#include <cpu_func.h>
Stefan Roesee3b9c982015-11-19 07:46:15 +010017#include <dm.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060018#include <log.h>
Stefan Roese19fc2ea2014-10-22 12:13:14 +020019#include <net.h>
20#include <netdev.h>
21#include <config.h>
22#include <malloc.h>
Simon Glass90526e92020-05-10 11:39:56 -060023#include <asm/cache.h>
Stefan Roese19fc2ea2014-10-22 12:13:14 +020024#include <asm/io.h>
Simon Glass336d4612020-02-03 07:36:16 -070025#include <dm/device_compat.h>
Simon Glass61b29b82020-02-03 07:36:15 -070026#include <dm/devres.h>
Simon Glasscd93d622020-05-10 11:40:13 -060027#include <linux/bitops.h>
Simon Glasseb41d8a2020-05-10 11:40:08 -060028#include <linux/bug.h>
Simon Glassc05ed002020-05-10 11:40:11 -060029#include <linux/delay.h>
Masahiro Yamada1221ce42016-09-21 11:28:55 +090030#include <linux/errno.h>
Stefan Roese19fc2ea2014-10-22 12:13:14 +020031#include <phy.h>
32#include <miiphy.h>
33#include <watchdog.h>
34#include <asm/arch/cpu.h>
35#include <asm/arch/soc.h>
36#include <linux/compat.h>
37#include <linux/mbus.h>
Aditya Prayoga18bfc8f2018-12-05 00:39:23 +080038#include <asm-generic/gpio.h>
Stefan Roese19fc2ea2014-10-22 12:13:14 +020039
Stefan Roesee3b9c982015-11-19 07:46:15 +010040DECLARE_GLOBAL_DATA_PTR;
41
Stefan Roese19fc2ea2014-10-22 12:13:14 +020042#if !defined(CONFIG_PHYLIB)
43# error Marvell mvneta requires PHYLIB
44#endif
45
Stefan Roese19fc2ea2014-10-22 12:13:14 +020046#define CONFIG_NR_CPUS 1
Stefan Roese19fc2ea2014-10-22 12:13:14 +020047#define ETH_HLEN 14 /* Total octets in header */
48
49/* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
50#define WRAP (2 + ETH_HLEN + 4 + 32)
51#define MTU 1500
52#define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
53
54#define MVNETA_SMI_TIMEOUT 10000
55
56/* Registers */
57#define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
58#define MVNETA_RXQ_HW_BUF_ALLOC BIT(1)
59#define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
60#define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
61#define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
62#define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
63#define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
64#define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
65#define MVNETA_RXQ_BUF_SIZE_SHIFT 19
66#define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
67#define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
68#define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
69#define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
70#define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
71#define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
72#define MVNETA_PORT_RX_RESET 0x1cc0
73#define MVNETA_PORT_RX_DMA_RESET BIT(0)
74#define MVNETA_PHY_ADDR 0x2000
75#define MVNETA_PHY_ADDR_MASK 0x1f
76#define MVNETA_SMI 0x2004
77#define MVNETA_PHY_REG_MASK 0x1f
78/* SMI register fields */
79#define MVNETA_SMI_DATA_OFFS 0 /* Data */
80#define MVNETA_SMI_DATA_MASK (0xffff << MVNETA_SMI_DATA_OFFS)
81#define MVNETA_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
82#define MVNETA_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr*/
83#define MVNETA_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
84#define MVNETA_SMI_OPCODE_READ (1 << MVNETA_SMI_OPCODE_OFFS)
85#define MVNETA_SMI_READ_VALID (1 << 27) /* Read Valid */
86#define MVNETA_SMI_BUSY (1 << 28) /* Busy */
87#define MVNETA_MBUS_RETRY 0x2010
88#define MVNETA_UNIT_INTR_CAUSE 0x2080
89#define MVNETA_UNIT_CONTROL 0x20B0
90#define MVNETA_PHY_POLLING_ENABLE BIT(1)
91#define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
92#define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
93#define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
Stefan Roese544eefe2016-05-19 17:46:36 +020094#define MVNETA_WIN_SIZE_MASK (0xffff0000)
Stefan Roese19fc2ea2014-10-22 12:13:14 +020095#define MVNETA_BASE_ADDR_ENABLE 0x2290
Stefan Roese544eefe2016-05-19 17:46:36 +020096#define MVNETA_BASE_ADDR_ENABLE_BIT 0x1
97#define MVNETA_PORT_ACCESS_PROTECT 0x2294
98#define MVNETA_PORT_ACCESS_PROTECT_WIN0_RW 0x3
Stefan Roese19fc2ea2014-10-22 12:13:14 +020099#define MVNETA_PORT_CONFIG 0x2400
100#define MVNETA_UNI_PROMISC_MODE BIT(0)
101#define MVNETA_DEF_RXQ(q) ((q) << 1)
102#define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
103#define MVNETA_TX_UNSET_ERR_SUM BIT(12)
104#define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
105#define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
106#define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
107#define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
108#define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
109 MVNETA_DEF_RXQ_ARP(q) | \
110 MVNETA_DEF_RXQ_TCP(q) | \
111 MVNETA_DEF_RXQ_UDP(q) | \
112 MVNETA_DEF_RXQ_BPDU(q) | \
113 MVNETA_TX_UNSET_ERR_SUM | \
114 MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
115#define MVNETA_PORT_CONFIG_EXTEND 0x2404
116#define MVNETA_MAC_ADDR_LOW 0x2414
117#define MVNETA_MAC_ADDR_HIGH 0x2418
118#define MVNETA_SDMA_CONFIG 0x241c
119#define MVNETA_SDMA_BRST_SIZE_16 4
120#define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
121#define MVNETA_RX_NO_DATA_SWAP BIT(4)
122#define MVNETA_TX_NO_DATA_SWAP BIT(5)
123#define MVNETA_DESC_SWAP BIT(6)
124#define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
125#define MVNETA_PORT_STATUS 0x2444
126#define MVNETA_TX_IN_PRGRS BIT(1)
127#define MVNETA_TX_FIFO_EMPTY BIT(8)
128#define MVNETA_RX_MIN_FRAME_SIZE 0x247c
129#define MVNETA_SERDES_CFG 0x24A0
130#define MVNETA_SGMII_SERDES_PROTO 0x0cc7
131#define MVNETA_QSGMII_SERDES_PROTO 0x0667
132#define MVNETA_TYPE_PRIO 0x24bc
133#define MVNETA_FORCE_UNI BIT(21)
134#define MVNETA_TXQ_CMD_1 0x24e4
135#define MVNETA_TXQ_CMD 0x2448
136#define MVNETA_TXQ_DISABLE_SHIFT 8
137#define MVNETA_TXQ_ENABLE_MASK 0x000000ff
138#define MVNETA_ACC_MODE 0x2500
139#define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
140#define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
141#define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
142#define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
143
144/* Exception Interrupt Port/Queue Cause register */
145
146#define MVNETA_INTR_NEW_CAUSE 0x25a0
147#define MVNETA_INTR_NEW_MASK 0x25a4
148
149/* bits 0..7 = TXQ SENT, one bit per queue.
150 * bits 8..15 = RXQ OCCUP, one bit per queue.
151 * bits 16..23 = RXQ FREE, one bit per queue.
152 * bit 29 = OLD_REG_SUM, see old reg ?
153 * bit 30 = TX_ERR_SUM, one bit for 4 ports
154 * bit 31 = MISC_SUM, one bit for 4 ports
155 */
156#define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
157#define MVNETA_TX_INTR_MASK_ALL (0xff << 0)
158#define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
159#define MVNETA_RX_INTR_MASK_ALL (0xff << 8)
160
161#define MVNETA_INTR_OLD_CAUSE 0x25a8
162#define MVNETA_INTR_OLD_MASK 0x25ac
163
164/* Data Path Port/Queue Cause Register */
165#define MVNETA_INTR_MISC_CAUSE 0x25b0
166#define MVNETA_INTR_MISC_MASK 0x25b4
167#define MVNETA_INTR_ENABLE 0x25b8
168
169#define MVNETA_RXQ_CMD 0x2680
170#define MVNETA_RXQ_DISABLE_SHIFT 8
171#define MVNETA_RXQ_ENABLE_MASK 0x000000ff
172#define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
173#define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
174#define MVNETA_GMAC_CTRL_0 0x2c00
175#define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
176#define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
177#define MVNETA_GMAC0_PORT_ENABLE BIT(0)
178#define MVNETA_GMAC_CTRL_2 0x2c08
179#define MVNETA_GMAC2_PCS_ENABLE BIT(3)
180#define MVNETA_GMAC2_PORT_RGMII BIT(4)
181#define MVNETA_GMAC2_PORT_RESET BIT(6)
182#define MVNETA_GMAC_STATUS 0x2c10
183#define MVNETA_GMAC_LINK_UP BIT(0)
184#define MVNETA_GMAC_SPEED_1000 BIT(1)
185#define MVNETA_GMAC_SPEED_100 BIT(2)
186#define MVNETA_GMAC_FULL_DUPLEX BIT(3)
187#define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
188#define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
189#define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
190#define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
191#define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
192#define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
193#define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
Konstantin Porotchkin278d30c2017-02-16 13:52:28 +0200194#define MVNETA_GMAC_FORCE_LINK_UP (BIT(0) | BIT(1))
195#define MVNETA_GMAC_IB_BYPASS_AN_EN BIT(3)
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200196#define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
197#define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
198#define MVNETA_GMAC_AN_SPEED_EN BIT(7)
Konstantin Porotchkin278d30c2017-02-16 13:52:28 +0200199#define MVNETA_GMAC_SET_FC_EN BIT(8)
200#define MVNETA_GMAC_ADVERT_FC_EN BIT(9)
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200201#define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
202#define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
Konstantin Porotchkin278d30c2017-02-16 13:52:28 +0200203#define MVNETA_GMAC_SAMPLE_TX_CFG_EN BIT(15)
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200204#define MVNETA_MIB_COUNTERS_BASE 0x3080
205#define MVNETA_MIB_LATE_COLLISION 0x7c
206#define MVNETA_DA_FILT_SPEC_MCAST 0x3400
207#define MVNETA_DA_FILT_OTH_MCAST 0x3500
208#define MVNETA_DA_FILT_UCAST_BASE 0x3600
209#define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
210#define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
211#define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
212#define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
213#define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
214#define MVNETA_TXQ_DEC_SENT_SHIFT 16
215#define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
216#define MVNETA_TXQ_SENT_DESC_SHIFT 16
217#define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
218#define MVNETA_PORT_TX_RESET 0x3cf0
219#define MVNETA_PORT_TX_DMA_RESET BIT(0)
220#define MVNETA_TX_MTU 0x3e0c
221#define MVNETA_TX_TOKEN_SIZE 0x3e14
222#define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
223#define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
224#define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
225
226/* Descriptor ring Macros */
227#define MVNETA_QUEUE_NEXT_DESC(q, index) \
228 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
229
230/* Various constants */
231
232/* Coalescing */
233#define MVNETA_TXDONE_COAL_PKTS 16
234#define MVNETA_RX_COAL_PKTS 32
235#define MVNETA_RX_COAL_USEC 100
236
237/* The two bytes Marvell header. Either contains a special value used
238 * by Marvell switches when a specific hardware mode is enabled (not
239 * supported by this driver) or is filled automatically by zeroes on
240 * the RX side. Those two bytes being at the front of the Ethernet
241 * header, they allow to have the IP header aligned on a 4 bytes
242 * boundary automatically: the hardware skips those two bytes on its
243 * own.
244 */
245#define MVNETA_MH_SIZE 2
246
247#define MVNETA_VLAN_TAG_LEN 4
248
249#define MVNETA_CPU_D_CACHE_LINE_SIZE 32
250#define MVNETA_TX_CSUM_MAX_SIZE 9800
251#define MVNETA_ACC_MODE_EXT 1
252
253/* Timeout constants */
254#define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
255#define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
256#define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
257
258#define MVNETA_TX_MTU_MAX 0x3ffff
259
260/* Max number of Rx descriptors */
261#define MVNETA_MAX_RXD 16
262
263/* Max number of Tx descriptors */
264#define MVNETA_MAX_TXD 16
265
266/* descriptor aligned size */
267#define MVNETA_DESC_ALIGNED_SIZE 32
268
269struct mvneta_port {
270 void __iomem *base;
271 struct mvneta_rx_queue *rxqs;
272 struct mvneta_tx_queue *txqs;
273
274 u8 mcast_count[256];
275 u16 tx_ring_size;
276 u16 rx_ring_size;
277
278 phy_interface_t phy_interface;
279 unsigned int link;
280 unsigned int duplex;
281 unsigned int speed;
282
283 int init;
284 int phyaddr;
285 struct phy_device *phydev;
Simon Glassbcee8d62019-12-06 21:41:35 -0700286#if CONFIG_IS_ENABLED(DM_GPIO)
Aditya Prayoga18bfc8f2018-12-05 00:39:23 +0800287 struct gpio_desc phy_reset_gpio;
288#endif
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200289 struct mii_dev *bus;
290};
291
292/* The mvneta_tx_desc and mvneta_rx_desc structures describe the
293 * layout of the transmit and reception DMA descriptors, and their
294 * layout is therefore defined by the hardware design
295 */
296
297#define MVNETA_TX_L3_OFF_SHIFT 0
298#define MVNETA_TX_IP_HLEN_SHIFT 8
299#define MVNETA_TX_L4_UDP BIT(16)
300#define MVNETA_TX_L3_IP6 BIT(17)
301#define MVNETA_TXD_IP_CSUM BIT(18)
302#define MVNETA_TXD_Z_PAD BIT(19)
303#define MVNETA_TXD_L_DESC BIT(20)
304#define MVNETA_TXD_F_DESC BIT(21)
305#define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
306 MVNETA_TXD_L_DESC | \
307 MVNETA_TXD_F_DESC)
308#define MVNETA_TX_L4_CSUM_FULL BIT(30)
309#define MVNETA_TX_L4_CSUM_NOT BIT(31)
310
311#define MVNETA_RXD_ERR_CRC 0x0
312#define MVNETA_RXD_ERR_SUMMARY BIT(16)
313#define MVNETA_RXD_ERR_OVERRUN BIT(17)
314#define MVNETA_RXD_ERR_LEN BIT(18)
315#define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
316#define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
317#define MVNETA_RXD_L3_IP4 BIT(25)
318#define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27))
319#define MVNETA_RXD_L4_CSUM_OK BIT(30)
320
321struct mvneta_tx_desc {
322 u32 command; /* Options used by HW for packet transmitting.*/
323 u16 reserverd1; /* csum_l4 (for future use) */
324 u16 data_size; /* Data size of transmitted packet in bytes */
325 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
326 u32 reserved2; /* hw_cmd - (for future use, PMT) */
327 u32 reserved3[4]; /* Reserved - (for future use) */
328};
329
330struct mvneta_rx_desc {
331 u32 status; /* Info about received packet */
332 u16 reserved1; /* pnc_info - (for future use, PnC) */
333 u16 data_size; /* Size of received packet in bytes */
334
335 u32 buf_phys_addr; /* Physical address of the buffer */
336 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
337
338 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
339 u16 reserved3; /* prefetch_cmd, for future use */
340 u16 reserved4; /* csum_l4 - (for future use, PnC) */
341
342 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
343 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
344};
345
346struct mvneta_tx_queue {
347 /* Number of this TX queue, in the range 0-7 */
348 u8 id;
349
350 /* Number of TX DMA descriptors in the descriptor ring */
351 int size;
352
353 /* Index of last TX DMA descriptor that was inserted */
354 int txq_put_index;
355
356 /* Index of the TX DMA descriptor to be cleaned up */
357 int txq_get_index;
358
359 /* Virtual address of the TX DMA descriptors array */
360 struct mvneta_tx_desc *descs;
361
362 /* DMA address of the TX DMA descriptors array */
363 dma_addr_t descs_phys;
364
365 /* Index of the last TX DMA descriptor */
366 int last_desc;
367
368 /* Index of the next TX DMA descriptor to process */
369 int next_desc_to_proc;
370};
371
372struct mvneta_rx_queue {
373 /* rx queue number, in the range 0-7 */
374 u8 id;
375
376 /* num of rx descriptors in the rx descriptor ring */
377 int size;
378
379 /* Virtual address of the RX DMA descriptors array */
380 struct mvneta_rx_desc *descs;
381
382 /* DMA address of the RX DMA descriptors array */
383 dma_addr_t descs_phys;
384
385 /* Index of the last RX DMA descriptor */
386 int last_desc;
387
388 /* Index of the next RX DMA descriptor to process */
389 int next_desc_to_proc;
390};
391
392/* U-Boot doesn't use the queues, so set the number to 1 */
393static int rxq_number = 1;
394static int txq_number = 1;
395static int rxq_def;
396
397struct buffer_location {
398 struct mvneta_tx_desc *tx_descs;
399 struct mvneta_rx_desc *rx_descs;
400 u32 rx_buffers;
401};
402
403/*
404 * All 4 interfaces use the same global buffer, since only one interface
405 * can be enabled at once
406 */
407static struct buffer_location buffer_loc;
408
409/*
410 * Page table entries are set to 1MB, or multiples of 1MB
411 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
412 */
413#define BD_SPACE (1 << 20)
414
Konstantin Porotchkin976feda2017-02-16 13:52:27 +0200415/*
416 * Dummy implementation that can be overwritten by a board
417 * specific function
418 */
419__weak int board_network_enable(struct mii_dev *bus)
420{
421 return 0;
422}
423
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200424/* Utility/helper methods */
425
426/* Write helper method */
427static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
428{
429 writel(data, pp->base + offset);
430}
431
432/* Read helper method */
433static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
434{
435 return readl(pp->base + offset);
436}
437
438/* Clear all MIB counters */
439static void mvneta_mib_counters_clear(struct mvneta_port *pp)
440{
441 int i;
442
443 /* Perform dummy reads from MIB counters */
444 for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4)
445 mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
446}
447
448/* Rx descriptors helper methods */
449
450/* Checks whether the RX descriptor having this status is both the first
451 * and the last descriptor for the RX packet. Each RX packet is currently
452 * received through a single RX descriptor, so not having each RX
453 * descriptor with its first and last bits set is an error
454 */
455static int mvneta_rxq_desc_is_first_last(u32 status)
456{
457 return (status & MVNETA_RXD_FIRST_LAST_DESC) ==
458 MVNETA_RXD_FIRST_LAST_DESC;
459}
460
461/* Add number of descriptors ready to receive new packets */
462static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp,
463 struct mvneta_rx_queue *rxq,
464 int ndescs)
465{
466 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
467 * be added at once
468 */
469 while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) {
470 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
471 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX <<
472 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
473 ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX;
474 }
475
476 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
477 (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
478}
479
480/* Get number of RX descriptors occupied by received packets */
481static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp,
482 struct mvneta_rx_queue *rxq)
483{
484 u32 val;
485
486 val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
487 return val & MVNETA_RXQ_OCCUPIED_ALL_MASK;
488}
489
490/* Update num of rx desc called upon return from rx path or
491 * from mvneta_rxq_drop_pkts().
492 */
493static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,
494 struct mvneta_rx_queue *rxq,
495 int rx_done, int rx_filled)
496{
497 u32 val;
498
499 if ((rx_done <= 0xff) && (rx_filled <= 0xff)) {
500 val = rx_done |
501 (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);
502 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
503 return;
504 }
505
506 /* Only 255 descriptors can be added at once */
507 while ((rx_done > 0) || (rx_filled > 0)) {
508 if (rx_done <= 0xff) {
509 val = rx_done;
510 rx_done = 0;
511 } else {
512 val = 0xff;
513 rx_done -= 0xff;
514 }
515 if (rx_filled <= 0xff) {
516 val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
517 rx_filled = 0;
518 } else {
519 val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
520 rx_filled -= 0xff;
521 }
522 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
523 }
524}
525
526/* Get pointer to next RX descriptor to be processed by SW */
527static struct mvneta_rx_desc *
528mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)
529{
530 int rx_desc = rxq->next_desc_to_proc;
531
532 rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc);
533 return rxq->descs + rx_desc;
534}
535
536/* Tx descriptors helper methods */
537
538/* Update HW with number of TX descriptors to be sent */
539static void mvneta_txq_pend_desc_add(struct mvneta_port *pp,
540 struct mvneta_tx_queue *txq,
541 int pend_desc)
542{
543 u32 val;
544
545 /* Only 255 descriptors can be added at once ; Assume caller
Heinrich Schuchardte4691562017-08-29 18:44:37 +0200546 * process TX descriptors in quanta less than 256
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200547 */
548 val = pend_desc;
549 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
550}
551
552/* Get pointer to next TX descriptor to be processed (send) by HW */
553static struct mvneta_tx_desc *
554mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq)
555{
556 int tx_desc = txq->next_desc_to_proc;
557
558 txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc);
559 return txq->descs + tx_desc;
560}
561
562/* Set rxq buf size */
563static void mvneta_rxq_buf_size_set(struct mvneta_port *pp,
564 struct mvneta_rx_queue *rxq,
565 int buf_size)
566{
567 u32 val;
568
569 val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
570
571 val &= ~MVNETA_RXQ_BUF_SIZE_MASK;
572 val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT);
573
574 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
575}
576
Konstantin Porotchkin278d30c2017-02-16 13:52:28 +0200577static int mvneta_port_is_fixed_link(struct mvneta_port *pp)
578{
579 /* phy_addr is set to invalid value for fixed link */
580 return pp->phyaddr > PHY_MAX_ADDR;
581}
582
583
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200584/* Start the Ethernet port RX and TX activity */
585static void mvneta_port_up(struct mvneta_port *pp)
586{
587 int queue;
588 u32 q_map;
589
590 /* Enable all initialized TXs. */
591 mvneta_mib_counters_clear(pp);
592 q_map = 0;
593 for (queue = 0; queue < txq_number; queue++) {
594 struct mvneta_tx_queue *txq = &pp->txqs[queue];
595 if (txq->descs != NULL)
596 q_map |= (1 << queue);
597 }
598 mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
599
600 /* Enable all initialized RXQs. */
601 q_map = 0;
602 for (queue = 0; queue < rxq_number; queue++) {
603 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
604 if (rxq->descs != NULL)
605 q_map |= (1 << queue);
606 }
607 mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
608}
609
610/* Stop the Ethernet port activity */
611static void mvneta_port_down(struct mvneta_port *pp)
612{
613 u32 val;
614 int count;
615
616 /* Stop Rx port activity. Check port Rx activity. */
617 val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
618
619 /* Issue stop command for active channels only */
620 if (val != 0)
621 mvreg_write(pp, MVNETA_RXQ_CMD,
622 val << MVNETA_RXQ_DISABLE_SHIFT);
623
624 /* Wait for all Rx activity to terminate. */
625 count = 0;
626 do {
627 if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
Sean Andersonc519cbf2020-09-15 10:44:55 -0400628 dev_warn(pp->phydev->dev,
629 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n",
630 val);
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200631 break;
632 }
633 mdelay(1);
634
635 val = mvreg_read(pp, MVNETA_RXQ_CMD);
636 } while (val & 0xff);
637
638 /* Stop Tx port activity. Check port Tx activity. Issue stop
639 * command for active channels only
640 */
641 val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
642
643 if (val != 0)
644 mvreg_write(pp, MVNETA_TXQ_CMD,
645 (val << MVNETA_TXQ_DISABLE_SHIFT));
646
647 /* Wait for all Tx activity to terminate. */
648 count = 0;
649 do {
650 if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
Sean Andersonc519cbf2020-09-15 10:44:55 -0400651 dev_warn(pp->phydev->dev,
652 "TIMEOUT for TX stopped status=0x%08x\n",
653 val);
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200654 break;
655 }
656 mdelay(1);
657
658 /* Check TX Command reg that all Txqs are stopped */
659 val = mvreg_read(pp, MVNETA_TXQ_CMD);
660
661 } while (val & 0xff);
662
663 /* Double check to verify that TX FIFO is empty */
664 count = 0;
665 do {
666 if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
Sean Andersonc519cbf2020-09-15 10:44:55 -0400667 dev_warn(pp->phydev->dev,
668 "TX FIFO empty timeout status=0x08%x\n",
669 val);
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200670 break;
671 }
672 mdelay(1);
673
674 val = mvreg_read(pp, MVNETA_PORT_STATUS);
675 } while (!(val & MVNETA_TX_FIFO_EMPTY) &&
676 (val & MVNETA_TX_IN_PRGRS));
677
678 udelay(200);
679}
680
681/* Enable the port by setting the port enable bit of the MAC control register */
682static void mvneta_port_enable(struct mvneta_port *pp)
683{
684 u32 val;
685
686 /* Enable port */
687 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
688 val |= MVNETA_GMAC0_PORT_ENABLE;
689 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
690}
691
692/* Disable the port and wait for about 200 usec before retuning */
693static void mvneta_port_disable(struct mvneta_port *pp)
694{
695 u32 val;
696
697 /* Reset the Enable bit in the Serial Control Register */
698 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
699 val &= ~MVNETA_GMAC0_PORT_ENABLE;
700 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
701
702 udelay(200);
703}
704
705/* Multicast tables methods */
706
707/* Set all entries in Unicast MAC Table; queue==-1 means reject all */
708static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue)
709{
710 int offset;
711 u32 val;
712
713 if (queue == -1) {
714 val = 0;
715 } else {
716 val = 0x1 | (queue << 1);
717 val |= (val << 24) | (val << 16) | (val << 8);
718 }
719
720 for (offset = 0; offset <= 0xc; offset += 4)
721 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
722}
723
724/* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
725static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue)
726{
727 int offset;
728 u32 val;
729
730 if (queue == -1) {
731 val = 0;
732 } else {
733 val = 0x1 | (queue << 1);
734 val |= (val << 24) | (val << 16) | (val << 8);
735 }
736
737 for (offset = 0; offset <= 0xfc; offset += 4)
738 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
739}
740
741/* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
742static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue)
743{
744 int offset;
745 u32 val;
746
747 if (queue == -1) {
748 memset(pp->mcast_count, 0, sizeof(pp->mcast_count));
749 val = 0;
750 } else {
751 memset(pp->mcast_count, 1, sizeof(pp->mcast_count));
752 val = 0x1 | (queue << 1);
753 val |= (val << 24) | (val << 16) | (val << 8);
754 }
755
756 for (offset = 0; offset <= 0xfc; offset += 4)
757 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
758}
759
760/* This method sets defaults to the NETA port:
761 * Clears interrupt Cause and Mask registers.
762 * Clears all MAC tables.
763 * Sets defaults to all registers.
764 * Resets RX and TX descriptor rings.
765 * Resets PHY.
766 * This method can be called after mvneta_port_down() to return the port
767 * settings to defaults.
768 */
769static void mvneta_defaults_set(struct mvneta_port *pp)
770{
771 int cpu;
772 int queue;
773 u32 val;
774
775 /* Clear all Cause registers */
776 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
777 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
778 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
779
780 /* Mask all interrupts */
781 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
782 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
783 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
784 mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
785
786 /* Enable MBUS Retry bit16 */
787 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
788
789 /* Set CPU queue access map - all CPUs have access to all RX
790 * queues and to all TX queues
791 */
792 for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++)
793 mvreg_write(pp, MVNETA_CPU_MAP(cpu),
794 (MVNETA_CPU_RXQ_ACCESS_ALL_MASK |
795 MVNETA_CPU_TXQ_ACCESS_ALL_MASK));
796
797 /* Reset RX and TX DMAs */
798 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
799 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
800
801 /* Disable Legacy WRR, Disable EJP, Release from reset */
802 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
803 for (queue = 0; queue < txq_number; queue++) {
804 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
805 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
806 }
807
808 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
809 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
810
811 /* Set Port Acceleration Mode */
812 val = MVNETA_ACC_MODE_EXT;
813 mvreg_write(pp, MVNETA_ACC_MODE, val);
814
815 /* Update val of portCfg register accordingly with all RxQueue types */
816 val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def);
817 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
818
819 val = 0;
820 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
821 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
822
823 /* Build PORT_SDMA_CONFIG_REG */
824 val = 0;
825
826 /* Default burst size */
827 val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
828 val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
829 val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP;
830
831 /* Assign port SDMA configuration */
832 mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
833
Konstantin Porotchkin278d30c2017-02-16 13:52:28 +0200834 /* Enable PHY polling in hardware if not in fixed-link mode */
835 if (!mvneta_port_is_fixed_link(pp)) {
836 val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
837 val |= MVNETA_PHY_POLLING_ENABLE;
838 mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
839 }
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200840
841 mvneta_set_ucast_table(pp, -1);
842 mvneta_set_special_mcast_table(pp, -1);
843 mvneta_set_other_mcast_table(pp, -1);
844}
845
846/* Set unicast address */
847static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble,
848 int queue)
849{
850 unsigned int unicast_reg;
851 unsigned int tbl_offset;
852 unsigned int reg_offset;
853
854 /* Locate the Unicast table entry */
855 last_nibble = (0xf & last_nibble);
856
857 /* offset from unicast tbl base */
858 tbl_offset = (last_nibble / 4) * 4;
859
860 /* offset within the above reg */
861 reg_offset = last_nibble % 4;
862
863 unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
864
865 if (queue == -1) {
866 /* Clear accepts frame bit at specified unicast DA tbl entry */
867 unicast_reg &= ~(0xff << (8 * reg_offset));
868 } else {
869 unicast_reg &= ~(0xff << (8 * reg_offset));
870 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
871 }
872
873 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
874}
875
876/* Set mac address */
877static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr,
878 int queue)
879{
880 unsigned int mac_h;
881 unsigned int mac_l;
882
883 if (queue != -1) {
884 mac_l = (addr[4] << 8) | (addr[5]);
885 mac_h = (addr[0] << 24) | (addr[1] << 16) |
886 (addr[2] << 8) | (addr[3] << 0);
887
888 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
889 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
890 }
891
892 /* Accept frames of this address */
893 mvneta_set_ucast_addr(pp, addr[5], queue);
894}
895
Matt Pelland0a85f022018-03-27 13:18:25 -0400896static int mvneta_write_hwaddr(struct udevice *dev)
897{
898 mvneta_mac_addr_set(dev_get_priv(dev),
Simon Glassc69cda22020-12-03 16:55:20 -0700899 ((struct eth_pdata *)dev_get_plat(dev))->enetaddr,
Matt Pelland0a85f022018-03-27 13:18:25 -0400900 rxq_def);
901
902 return 0;
903}
904
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200905/* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
906static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
907 u32 phys_addr, u32 cookie)
908{
909 rx_desc->buf_cookie = cookie;
910 rx_desc->buf_phys_addr = phys_addr;
911}
912
913/* Decrement sent descriptors counter */
914static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp,
915 struct mvneta_tx_queue *txq,
916 int sent_desc)
917{
918 u32 val;
919
920 /* Only 255 TX descriptors can be updated at once */
921 while (sent_desc > 0xff) {
922 val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT;
923 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
924 sent_desc = sent_desc - 0xff;
925 }
926
927 val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT;
928 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
929}
930
931/* Get number of TX descriptors already sent by HW */
932static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp,
933 struct mvneta_tx_queue *txq)
934{
935 u32 val;
936 int sent_desc;
937
938 val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
939 sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >>
940 MVNETA_TXQ_SENT_DESC_SHIFT;
941
942 return sent_desc;
943}
944
945/* Display more error info */
946static void mvneta_rx_error(struct mvneta_port *pp,
947 struct mvneta_rx_desc *rx_desc)
948{
949 u32 status = rx_desc->status;
950
951 if (!mvneta_rxq_desc_is_first_last(status)) {
Sean Andersonc519cbf2020-09-15 10:44:55 -0400952 dev_err(pp->phydev->dev,
953 "bad rx status %08x (buffer oversize), size=%d\n",
954 status, rx_desc->data_size);
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200955 return;
956 }
957
958 switch (status & MVNETA_RXD_ERR_CODE_MASK) {
959 case MVNETA_RXD_ERR_CRC:
Sean Andersonc519cbf2020-09-15 10:44:55 -0400960 dev_err(pp->phydev->dev,
961 "bad rx status %08x (crc error), size=%d\n", status,
962 rx_desc->data_size);
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200963 break;
964 case MVNETA_RXD_ERR_OVERRUN:
Sean Andersonc519cbf2020-09-15 10:44:55 -0400965 dev_err(pp->phydev->dev,
966 "bad rx status %08x (overrun error), size=%d\n", status,
967 rx_desc->data_size);
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200968 break;
969 case MVNETA_RXD_ERR_LEN:
Sean Andersonc519cbf2020-09-15 10:44:55 -0400970 dev_err(pp->phydev->dev,
971 "bad rx status %08x (max frame length error), size=%d\n",
972 status, rx_desc->data_size);
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200973 break;
974 case MVNETA_RXD_ERR_RESOURCE:
Sean Andersonc519cbf2020-09-15 10:44:55 -0400975 dev_err(pp->phydev->dev,
976 "bad rx status %08x (resource error), size=%d\n",
977 status, rx_desc->data_size);
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200978 break;
979 }
980}
981
982static struct mvneta_rx_queue *mvneta_rxq_handle_get(struct mvneta_port *pp,
983 int rxq)
984{
985 return &pp->rxqs[rxq];
986}
987
988
989/* Drop packets received by the RXQ and free buffers */
990static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
991 struct mvneta_rx_queue *rxq)
992{
993 int rx_done;
994
995 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
996 if (rx_done)
997 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
998}
999
1000/* Handle rxq fill: allocates rxq skbs; called when initializing a port */
1001static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
1002 int num)
1003{
1004 int i;
1005
1006 for (i = 0; i < num; i++) {
1007 u32 addr;
1008
1009 /* U-Boot special: Fill in the rx buffer addresses */
1010 addr = buffer_loc.rx_buffers + (i * RX_BUFFER_SIZE);
1011 mvneta_rx_desc_fill(rxq->descs + i, addr, addr);
1012 }
1013
1014 /* Add this number of RX descriptors as non occupied (ready to
1015 * get packets)
1016 */
1017 mvneta_rxq_non_occup_desc_add(pp, rxq, i);
1018
1019 return 0;
1020}
1021
1022/* Rx/Tx queue initialization/cleanup methods */
1023
1024/* Create a specified RX queue */
1025static int mvneta_rxq_init(struct mvneta_port *pp,
1026 struct mvneta_rx_queue *rxq)
1027
1028{
1029 rxq->size = pp->rx_ring_size;
1030
1031 /* Allocate memory for RX descriptors */
1032 rxq->descs_phys = (dma_addr_t)rxq->descs;
1033 if (rxq->descs == NULL)
1034 return -ENOMEM;
1035
Jon Nettleton199b27b2018-05-30 08:52:29 +03001036 WARN_ON(rxq->descs != PTR_ALIGN(rxq->descs, ARCH_DMA_MINALIGN));
1037
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001038 rxq->last_desc = rxq->size - 1;
1039
1040 /* Set Rx descriptors queue starting address */
1041 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
1042 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
1043
1044 /* Fill RXQ with buffers from RX pool */
1045 mvneta_rxq_buf_size_set(pp, rxq, RX_BUFFER_SIZE);
1046 mvneta_rxq_fill(pp, rxq, rxq->size);
1047
1048 return 0;
1049}
1050
1051/* Cleanup Rx queue */
1052static void mvneta_rxq_deinit(struct mvneta_port *pp,
1053 struct mvneta_rx_queue *rxq)
1054{
1055 mvneta_rxq_drop_pkts(pp, rxq);
1056
1057 rxq->descs = NULL;
1058 rxq->last_desc = 0;
1059 rxq->next_desc_to_proc = 0;
1060 rxq->descs_phys = 0;
1061}
1062
1063/* Create and initialize a tx queue */
1064static int mvneta_txq_init(struct mvneta_port *pp,
1065 struct mvneta_tx_queue *txq)
1066{
1067 txq->size = pp->tx_ring_size;
1068
1069 /* Allocate memory for TX descriptors */
Stefan Roese3cbc11d2016-05-19 18:09:17 +02001070 txq->descs_phys = (dma_addr_t)txq->descs;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001071 if (txq->descs == NULL)
1072 return -ENOMEM;
1073
Jon Nettleton199b27b2018-05-30 08:52:29 +03001074 WARN_ON(txq->descs != PTR_ALIGN(txq->descs, ARCH_DMA_MINALIGN));
1075
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001076 txq->last_desc = txq->size - 1;
1077
1078 /* Set maximum bandwidth for enabled TXQs */
1079 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
1080 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
1081
1082 /* Set Tx descriptors queue starting address */
1083 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
1084 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
1085
1086 return 0;
1087}
1088
1089/* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
1090static void mvneta_txq_deinit(struct mvneta_port *pp,
1091 struct mvneta_tx_queue *txq)
1092{
1093 txq->descs = NULL;
1094 txq->last_desc = 0;
1095 txq->next_desc_to_proc = 0;
1096 txq->descs_phys = 0;
1097
1098 /* Set minimum bandwidth for disabled TXQs */
1099 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
1100 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
1101
1102 /* Set Tx descriptors queue starting address and size */
1103 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
1104 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
1105}
1106
1107/* Cleanup all Tx queues */
1108static void mvneta_cleanup_txqs(struct mvneta_port *pp)
1109{
1110 int queue;
1111
1112 for (queue = 0; queue < txq_number; queue++)
1113 mvneta_txq_deinit(pp, &pp->txqs[queue]);
1114}
1115
1116/* Cleanup all Rx queues */
1117static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
1118{
1119 int queue;
1120
1121 for (queue = 0; queue < rxq_number; queue++)
1122 mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
1123}
1124
1125
1126/* Init all Rx queues */
1127static int mvneta_setup_rxqs(struct mvneta_port *pp)
1128{
1129 int queue;
1130
1131 for (queue = 0; queue < rxq_number; queue++) {
1132 int err = mvneta_rxq_init(pp, &pp->rxqs[queue]);
1133 if (err) {
Sean Andersonc519cbf2020-09-15 10:44:55 -04001134 dev_err(pp->phydev->dev, "%s: can't create rxq=%d\n",
1135 __func__, queue);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001136 mvneta_cleanup_rxqs(pp);
1137 return err;
1138 }
1139 }
1140
1141 return 0;
1142}
1143
1144/* Init all tx queues */
1145static int mvneta_setup_txqs(struct mvneta_port *pp)
1146{
1147 int queue;
1148
1149 for (queue = 0; queue < txq_number; queue++) {
1150 int err = mvneta_txq_init(pp, &pp->txqs[queue]);
1151 if (err) {
Sean Andersonc519cbf2020-09-15 10:44:55 -04001152 dev_err(pp->phydev->dev, "%s: can't create txq=%d\n",
1153 __func__, queue);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001154 mvneta_cleanup_txqs(pp);
1155 return err;
1156 }
1157 }
1158
1159 return 0;
1160}
1161
1162static void mvneta_start_dev(struct mvneta_port *pp)
1163{
1164 /* start the Rx/Tx activity */
1165 mvneta_port_enable(pp);
1166}
1167
Stefan Roesee3b9c982015-11-19 07:46:15 +01001168static void mvneta_adjust_link(struct udevice *dev)
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001169{
Stefan Roesee3b9c982015-11-19 07:46:15 +01001170 struct mvneta_port *pp = dev_get_priv(dev);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001171 struct phy_device *phydev = pp->phydev;
1172 int status_change = 0;
1173
Konstantin Porotchkin278d30c2017-02-16 13:52:28 +02001174 if (mvneta_port_is_fixed_link(pp)) {
1175 debug("Using fixed link, skip link adjust\n");
1176 return;
1177 }
1178
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001179 if (phydev->link) {
1180 if ((pp->speed != phydev->speed) ||
1181 (pp->duplex != phydev->duplex)) {
1182 u32 val;
1183
1184 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
1185 val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
1186 MVNETA_GMAC_CONFIG_GMII_SPEED |
1187 MVNETA_GMAC_CONFIG_FULL_DUPLEX |
1188 MVNETA_GMAC_AN_SPEED_EN |
1189 MVNETA_GMAC_AN_DUPLEX_EN);
1190
1191 if (phydev->duplex)
1192 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
1193
1194 if (phydev->speed == SPEED_1000)
1195 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
1196 else
1197 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
1198
1199 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
1200
1201 pp->duplex = phydev->duplex;
1202 pp->speed = phydev->speed;
1203 }
1204 }
1205
1206 if (phydev->link != pp->link) {
1207 if (!phydev->link) {
1208 pp->duplex = -1;
1209 pp->speed = 0;
1210 }
1211
1212 pp->link = phydev->link;
1213 status_change = 1;
1214 }
1215
1216 if (status_change) {
1217 if (phydev->link) {
1218 u32 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
1219 val |= (MVNETA_GMAC_FORCE_LINK_PASS |
1220 MVNETA_GMAC_FORCE_LINK_DOWN);
1221 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
1222 mvneta_port_up(pp);
1223 } else {
1224 mvneta_port_down(pp);
1225 }
1226 }
1227}
1228
Stefan Roesee3b9c982015-11-19 07:46:15 +01001229static int mvneta_open(struct udevice *dev)
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001230{
Stefan Roesee3b9c982015-11-19 07:46:15 +01001231 struct mvneta_port *pp = dev_get_priv(dev);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001232 int ret;
1233
1234 ret = mvneta_setup_rxqs(pp);
1235 if (ret)
1236 return ret;
1237
1238 ret = mvneta_setup_txqs(pp);
1239 if (ret)
1240 return ret;
1241
1242 mvneta_adjust_link(dev);
1243
1244 mvneta_start_dev(pp);
1245
1246 return 0;
1247}
1248
1249/* Initialize hw */
Stefan Roesee3b9c982015-11-19 07:46:15 +01001250static int mvneta_init2(struct mvneta_port *pp)
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001251{
1252 int queue;
1253
1254 /* Disable port */
1255 mvneta_port_disable(pp);
1256
1257 /* Set port default values */
1258 mvneta_defaults_set(pp);
1259
1260 pp->txqs = kzalloc(txq_number * sizeof(struct mvneta_tx_queue),
1261 GFP_KERNEL);
1262 if (!pp->txqs)
1263 return -ENOMEM;
1264
1265 /* U-Boot special: use preallocated area */
1266 pp->txqs[0].descs = buffer_loc.tx_descs;
1267
1268 /* Initialize TX descriptor rings */
1269 for (queue = 0; queue < txq_number; queue++) {
1270 struct mvneta_tx_queue *txq = &pp->txqs[queue];
1271 txq->id = queue;
1272 txq->size = pp->tx_ring_size;
1273 }
1274
1275 pp->rxqs = kzalloc(rxq_number * sizeof(struct mvneta_rx_queue),
1276 GFP_KERNEL);
1277 if (!pp->rxqs) {
1278 kfree(pp->txqs);
1279 return -ENOMEM;
1280 }
1281
1282 /* U-Boot special: use preallocated area */
1283 pp->rxqs[0].descs = buffer_loc.rx_descs;
1284
1285 /* Create Rx descriptor rings */
1286 for (queue = 0; queue < rxq_number; queue++) {
1287 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
1288 rxq->id = queue;
1289 rxq->size = pp->rx_ring_size;
1290 }
1291
1292 return 0;
1293}
1294
1295/* platform glue : initialize decoding windows */
Stefan Roese544eefe2016-05-19 17:46:36 +02001296
1297/*
1298 * Not like A380, in Armada3700, there are two layers of decode windows for GBE:
1299 * First layer is: GbE Address window that resides inside the GBE unit,
1300 * Second layer is: Fabric address window which is located in the NIC400
1301 * (South Fabric).
1302 * To simplify the address decode configuration for Armada3700, we bypass the
1303 * first layer of GBE decode window by setting the first window to 4GB.
1304 */
1305static void mvneta_bypass_mbus_windows(struct mvneta_port *pp)
1306{
1307 /*
1308 * Set window size to 4GB, to bypass GBE address decode, leave the
1309 * work to MBUS decode window
1310 */
1311 mvreg_write(pp, MVNETA_WIN_SIZE(0), MVNETA_WIN_SIZE_MASK);
1312
1313 /* Enable GBE address decode window 0 by set bit 0 to 0 */
1314 clrbits_le32(pp->base + MVNETA_BASE_ADDR_ENABLE,
1315 MVNETA_BASE_ADDR_ENABLE_BIT);
1316
1317 /* Set GBE address decode window 0 to full Access (read or write) */
1318 setbits_le32(pp->base + MVNETA_PORT_ACCESS_PROTECT,
1319 MVNETA_PORT_ACCESS_PROTECT_WIN0_RW);
1320}
1321
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001322static void mvneta_conf_mbus_windows(struct mvneta_port *pp)
1323{
1324 const struct mbus_dram_target_info *dram;
1325 u32 win_enable;
1326 u32 win_protect;
1327 int i;
1328
1329 dram = mvebu_mbus_dram_info();
1330 for (i = 0; i < 6; i++) {
1331 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
1332 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
1333
1334 if (i < 4)
1335 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
1336 }
1337
1338 win_enable = 0x3f;
1339 win_protect = 0;
1340
1341 for (i = 0; i < dram->num_cs; i++) {
1342 const struct mbus_dram_window *cs = dram->cs + i;
1343 mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) |
1344 (cs->mbus_attr << 8) | dram->mbus_dram_target_id);
1345
1346 mvreg_write(pp, MVNETA_WIN_SIZE(i),
1347 (cs->size - 1) & 0xffff0000);
1348
1349 win_enable &= ~(1 << i);
1350 win_protect |= 3 << (2 * i);
1351 }
1352
1353 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
1354}
1355
1356/* Power up the port */
1357static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
1358{
1359 u32 ctrl;
1360
1361 /* MAC Cause register should be cleared */
1362 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
1363
1364 ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
1365
1366 /* Even though it might look weird, when we're configured in
1367 * SGMII or QSGMII mode, the RGMII bit needs to be set.
1368 */
1369 switch (phy_mode) {
1370 case PHY_INTERFACE_MODE_QSGMII:
1371 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO);
1372 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
1373 break;
1374 case PHY_INTERFACE_MODE_SGMII:
1375 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
1376 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
1377 break;
1378 case PHY_INTERFACE_MODE_RGMII:
1379 case PHY_INTERFACE_MODE_RGMII_ID:
1380 ctrl |= MVNETA_GMAC2_PORT_RGMII;
1381 break;
1382 default:
1383 return -EINVAL;
1384 }
1385
1386 /* Cancel Port Reset */
1387 ctrl &= ~MVNETA_GMAC2_PORT_RESET;
1388 mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl);
1389
1390 while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
1391 MVNETA_GMAC2_PORT_RESET) != 0)
1392 continue;
1393
1394 return 0;
1395}
1396
1397/* Device initialization routine */
Stefan Roesee3b9c982015-11-19 07:46:15 +01001398static int mvneta_init(struct udevice *dev)
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001399{
Simon Glassc69cda22020-12-03 16:55:20 -07001400 struct eth_pdata *pdata = dev_get_plat(dev);
Stefan Roesee3b9c982015-11-19 07:46:15 +01001401 struct mvneta_port *pp = dev_get_priv(dev);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001402 int err;
1403
1404 pp->tx_ring_size = MVNETA_MAX_TXD;
1405 pp->rx_ring_size = MVNETA_MAX_RXD;
1406
Stefan Roesee3b9c982015-11-19 07:46:15 +01001407 err = mvneta_init2(pp);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001408 if (err < 0) {
Sean Anderson13cbe292020-09-15 10:44:54 -04001409 dev_err(dev, "can't init eth hal\n");
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001410 return err;
1411 }
1412
Stefan Roesee3b9c982015-11-19 07:46:15 +01001413 mvneta_mac_addr_set(pp, pdata->enetaddr, rxq_def);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001414
1415 err = mvneta_port_power_up(pp, pp->phy_interface);
1416 if (err < 0) {
Sean Anderson13cbe292020-09-15 10:44:54 -04001417 dev_err(dev, "can't power up port\n");
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001418 return err;
1419 }
1420
1421 /* Call open() now as it needs to be done before runing send() */
1422 mvneta_open(dev);
1423
1424 return 0;
1425}
1426
1427/* U-Boot only functions follow here */
1428
1429/* SMI / MDIO functions */
1430
1431static int smi_wait_ready(struct mvneta_port *pp)
1432{
1433 u32 timeout = MVNETA_SMI_TIMEOUT;
1434 u32 smi_reg;
1435
1436 /* wait till the SMI is not busy */
1437 do {
1438 /* read smi register */
1439 smi_reg = mvreg_read(pp, MVNETA_SMI);
1440 if (timeout-- == 0) {
1441 printf("Error: SMI busy timeout\n");
1442 return -EFAULT;
1443 }
1444 } while (smi_reg & MVNETA_SMI_BUSY);
1445
1446 return 0;
1447}
1448
1449/*
Stefan Roesee3b9c982015-11-19 07:46:15 +01001450 * mvneta_mdio_read - miiphy_read callback function.
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001451 *
1452 * Returns 16bit phy register value, or 0xffff on error
1453 */
Stefan Roesee3b9c982015-11-19 07:46:15 +01001454static int mvneta_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001455{
Stefan Roesee3b9c982015-11-19 07:46:15 +01001456 struct mvneta_port *pp = bus->priv;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001457 u32 smi_reg;
1458 u32 timeout;
1459
1460 /* check parameters */
Stefan Roesee3b9c982015-11-19 07:46:15 +01001461 if (addr > MVNETA_PHY_ADDR_MASK) {
1462 printf("Error: Invalid PHY address %d\n", addr);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001463 return -EFAULT;
1464 }
1465
Stefan Roesee3b9c982015-11-19 07:46:15 +01001466 if (reg > MVNETA_PHY_REG_MASK) {
1467 printf("Err: Invalid register offset %d\n", reg);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001468 return -EFAULT;
1469 }
1470
1471 /* wait till the SMI is not busy */
1472 if (smi_wait_ready(pp) < 0)
1473 return -EFAULT;
1474
1475 /* fill the phy address and regiser offset and read opcode */
Stefan Roesee3b9c982015-11-19 07:46:15 +01001476 smi_reg = (addr << MVNETA_SMI_DEV_ADDR_OFFS)
1477 | (reg << MVNETA_SMI_REG_ADDR_OFFS)
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001478 | MVNETA_SMI_OPCODE_READ;
1479
1480 /* write the smi register */
1481 mvreg_write(pp, MVNETA_SMI, smi_reg);
1482
Stefan Roesee3b9c982015-11-19 07:46:15 +01001483 /* wait till read value is ready */
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001484 timeout = MVNETA_SMI_TIMEOUT;
1485
1486 do {
1487 /* read smi register */
1488 smi_reg = mvreg_read(pp, MVNETA_SMI);
1489 if (timeout-- == 0) {
1490 printf("Err: SMI read ready timeout\n");
1491 return -EFAULT;
1492 }
1493 } while (!(smi_reg & MVNETA_SMI_READ_VALID));
1494
1495 /* Wait for the data to update in the SMI register */
1496 for (timeout = 0; timeout < MVNETA_SMI_TIMEOUT; timeout++)
1497 ;
1498
Stefan Roesee3b9c982015-11-19 07:46:15 +01001499 return mvreg_read(pp, MVNETA_SMI) & MVNETA_SMI_DATA_MASK;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001500}
1501
1502/*
Stefan Roesee3b9c982015-11-19 07:46:15 +01001503 * mvneta_mdio_write - miiphy_write callback function.
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001504 *
1505 * Returns 0 if write succeed, -EINVAL on bad parameters
1506 * -ETIME on timeout
1507 */
Stefan Roesee3b9c982015-11-19 07:46:15 +01001508static int mvneta_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
1509 u16 value)
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001510{
Stefan Roesee3b9c982015-11-19 07:46:15 +01001511 struct mvneta_port *pp = bus->priv;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001512 u32 smi_reg;
1513
1514 /* check parameters */
Stefan Roesee3b9c982015-11-19 07:46:15 +01001515 if (addr > MVNETA_PHY_ADDR_MASK) {
1516 printf("Error: Invalid PHY address %d\n", addr);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001517 return -EFAULT;
1518 }
1519
Stefan Roesee3b9c982015-11-19 07:46:15 +01001520 if (reg > MVNETA_PHY_REG_MASK) {
1521 printf("Err: Invalid register offset %d\n", reg);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001522 return -EFAULT;
1523 }
1524
1525 /* wait till the SMI is not busy */
1526 if (smi_wait_ready(pp) < 0)
1527 return -EFAULT;
1528
1529 /* fill the phy addr and reg offset and write opcode and data */
Stefan Roesee3b9c982015-11-19 07:46:15 +01001530 smi_reg = value << MVNETA_SMI_DATA_OFFS;
1531 smi_reg |= (addr << MVNETA_SMI_DEV_ADDR_OFFS)
1532 | (reg << MVNETA_SMI_REG_ADDR_OFFS);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001533 smi_reg &= ~MVNETA_SMI_OPCODE_READ;
1534
1535 /* write the smi register */
1536 mvreg_write(pp, MVNETA_SMI, smi_reg);
1537
1538 return 0;
1539}
1540
Stefan Roesee3b9c982015-11-19 07:46:15 +01001541static int mvneta_start(struct udevice *dev)
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001542{
Stefan Roesee3b9c982015-11-19 07:46:15 +01001543 struct mvneta_port *pp = dev_get_priv(dev);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001544 struct phy_device *phydev;
1545
1546 mvneta_port_power_up(pp, pp->phy_interface);
1547
1548 if (!pp->init || pp->link == 0) {
Konstantin Porotchkin278d30c2017-02-16 13:52:28 +02001549 if (mvneta_port_is_fixed_link(pp)) {
1550 u32 val;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001551
Konstantin Porotchkin278d30c2017-02-16 13:52:28 +02001552 pp->init = 1;
1553 pp->link = 1;
1554 mvneta_init(dev);
1555
1556 val = MVNETA_GMAC_FORCE_LINK_UP |
1557 MVNETA_GMAC_IB_BYPASS_AN_EN |
1558 MVNETA_GMAC_SET_FC_EN |
1559 MVNETA_GMAC_ADVERT_FC_EN |
1560 MVNETA_GMAC_SAMPLE_TX_CFG_EN;
1561
1562 if (pp->duplex)
1563 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
1564
1565 if (pp->speed == SPEED_1000)
1566 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
1567 else if (pp->speed == SPEED_100)
1568 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
1569
1570 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
1571 } else {
1572 /* Set phy address of the port */
1573 mvreg_write(pp, MVNETA_PHY_ADDR, pp->phyaddr);
1574
1575 phydev = phy_connect(pp->bus, pp->phyaddr, dev,
1576 pp->phy_interface);
Marek Behúncf2cf852018-04-24 17:21:29 +02001577 if (!phydev) {
1578 printf("phy_connect failed\n");
1579 return -ENODEV;
1580 }
Konstantin Porotchkin278d30c2017-02-16 13:52:28 +02001581
1582 pp->phydev = phydev;
1583 phy_config(phydev);
1584 phy_startup(phydev);
1585 if (!phydev->link) {
1586 printf("%s: No link.\n", phydev->dev->name);
1587 return -1;
1588 }
1589
1590 /* Full init on first call */
1591 mvneta_init(dev);
1592 pp->init = 1;
1593 return 0;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001594 }
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001595 }
1596
Konstantin Porotchkin278d30c2017-02-16 13:52:28 +02001597 /* Upon all following calls, this is enough */
1598 mvneta_port_up(pp);
1599 mvneta_port_enable(pp);
1600
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001601 return 0;
1602}
1603
Stefan Roesee3b9c982015-11-19 07:46:15 +01001604static int mvneta_send(struct udevice *dev, void *packet, int length)
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001605{
Stefan Roesee3b9c982015-11-19 07:46:15 +01001606 struct mvneta_port *pp = dev_get_priv(dev);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001607 struct mvneta_tx_queue *txq = &pp->txqs[0];
1608 struct mvneta_tx_desc *tx_desc;
1609 int sent_desc;
1610 u32 timeout = 0;
1611
1612 /* Get a descriptor for the first part of the packet */
1613 tx_desc = mvneta_txq_next_desc_get(txq);
1614
Stefan Roese3cbc11d2016-05-19 18:09:17 +02001615 tx_desc->buf_phys_addr = (u32)(uintptr_t)packet;
Stefan Roesee3b9c982015-11-19 07:46:15 +01001616 tx_desc->data_size = length;
Stefan Roese3cbc11d2016-05-19 18:09:17 +02001617 flush_dcache_range((ulong)packet,
1618 (ulong)packet + ALIGN(length, PKTALIGN));
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001619
1620 /* First and Last descriptor */
1621 tx_desc->command = MVNETA_TX_L4_CSUM_NOT | MVNETA_TXD_FLZ_DESC;
1622 mvneta_txq_pend_desc_add(pp, txq, 1);
1623
1624 /* Wait for packet to be sent (queue might help with speed here) */
1625 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
1626 while (!sent_desc) {
1627 if (timeout++ > 10000) {
1628 printf("timeout: packet not sent\n");
1629 return -1;
1630 }
1631 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
1632 }
1633
1634 /* txDone has increased - hw sent packet */
1635 mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001636
1637 return 0;
1638}
1639
Stefan Roesee3b9c982015-11-19 07:46:15 +01001640static int mvneta_recv(struct udevice *dev, int flags, uchar **packetp)
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001641{
Stefan Roesee3b9c982015-11-19 07:46:15 +01001642 struct mvneta_port *pp = dev_get_priv(dev);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001643 int rx_done;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001644 struct mvneta_rx_queue *rxq;
Stefan Roesee3b9c982015-11-19 07:46:15 +01001645 int rx_bytes = 0;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001646
1647 /* get rx queue */
1648 rxq = mvneta_rxq_handle_get(pp, rxq_def);
1649 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001650
Stefan Roesee3b9c982015-11-19 07:46:15 +01001651 if (rx_done) {
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001652 struct mvneta_rx_desc *rx_desc;
1653 unsigned char *data;
1654 u32 rx_status;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001655
1656 /*
1657 * No cache invalidation needed here, since the desc's are
1658 * located in a uncached memory region
1659 */
1660 rx_desc = mvneta_rxq_next_desc_get(rxq);
1661
1662 rx_status = rx_desc->status;
1663 if (!mvneta_rxq_desc_is_first_last(rx_status) ||
1664 (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
1665 mvneta_rx_error(pp, rx_desc);
1666 /* leave the descriptor untouched */
Stefan Roesee3b9c982015-11-19 07:46:15 +01001667 return -EIO;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001668 }
1669
1670 /* 2 bytes for marvell header. 4 bytes for crc */
1671 rx_bytes = rx_desc->data_size - 6;
1672
1673 /* give packet to stack - skip on first 2 bytes */
Stefan Roese3cbc11d2016-05-19 18:09:17 +02001674 data = (u8 *)(uintptr_t)rx_desc->buf_cookie + 2;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001675 /*
1676 * No cache invalidation needed here, since the rx_buffer's are
1677 * located in a uncached memory region
1678 */
Stefan Roesee3b9c982015-11-19 07:46:15 +01001679 *packetp = data;
1680
Jason Brown32ac8b02017-11-28 11:12:43 -08001681 /*
1682 * Only mark one descriptor as free
1683 * since only one was processed
1684 */
1685 mvneta_rxq_desc_num_update(pp, rxq, 1, 1);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001686 }
1687
Stefan Roesee3b9c982015-11-19 07:46:15 +01001688 return rx_bytes;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001689}
1690
Stefan Roesee3b9c982015-11-19 07:46:15 +01001691static int mvneta_probe(struct udevice *dev)
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001692{
Simon Glassc69cda22020-12-03 16:55:20 -07001693 struct eth_pdata *pdata = dev_get_plat(dev);
Stefan Roesee3b9c982015-11-19 07:46:15 +01001694 struct mvneta_port *pp = dev_get_priv(dev);
1695 void *blob = (void *)gd->fdt_blob;
Simon Glasse160f7d2017-01-17 16:52:55 -07001696 int node = dev_of_offset(dev);
Stefan Roesee3b9c982015-11-19 07:46:15 +01001697 struct mii_dev *bus;
1698 unsigned long addr;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001699 void *bd_space;
Konstantin Porotchkin976feda2017-02-16 13:52:27 +02001700 int ret;
Konstantin Porotchkin278d30c2017-02-16 13:52:28 +02001701 int fl_node;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001702
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001703 /*
1704 * Allocate buffer area for descs and rx_buffers. This is only
1705 * done once for all interfaces. As only one interface can
Chris Packham6723b232016-08-29 20:54:02 +12001706 * be active. Make this area DMA safe by disabling the D-cache
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001707 */
1708 if (!buffer_loc.tx_descs) {
Jon Nettleton199b27b2018-05-30 08:52:29 +03001709 u32 size;
1710
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001711 /* Align buffer area for descs and rx_buffers to 1MiB */
1712 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
Rabeeh Khoury0f8888b2018-06-19 21:36:50 +03001713 flush_dcache_range((ulong)bd_space, (ulong)bd_space + BD_SPACE);
Stefan Roese3cbc11d2016-05-19 18:09:17 +02001714 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, BD_SPACE,
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001715 DCACHE_OFF);
1716 buffer_loc.tx_descs = (struct mvneta_tx_desc *)bd_space;
Jon Nettleton199b27b2018-05-30 08:52:29 +03001717 size = roundup(MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc),
1718 ARCH_DMA_MINALIGN);
Rabeeh Khoury318b5d72018-06-19 21:36:51 +03001719 memset(buffer_loc.tx_descs, 0, size);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001720 buffer_loc.rx_descs = (struct mvneta_rx_desc *)
Jon Nettleton199b27b2018-05-30 08:52:29 +03001721 ((phys_addr_t)bd_space + size);
1722 size += roundup(MVNETA_MAX_RXD * sizeof(struct mvneta_rx_desc),
1723 ARCH_DMA_MINALIGN);
1724 buffer_loc.rx_buffers = (phys_addr_t)(bd_space + size);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001725 }
1726
Stefan Roesee3b9c982015-11-19 07:46:15 +01001727 pp->base = (void __iomem *)pdata->iobase;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001728
Stefan Roesee3b9c982015-11-19 07:46:15 +01001729 /* Configure MBUS address windows */
Simon Glass911f3ae2017-05-18 20:08:57 -06001730 if (device_is_compatible(dev, "marvell,armada-3700-neta"))
Stefan Roese544eefe2016-05-19 17:46:36 +02001731 mvneta_bypass_mbus_windows(pp);
1732 else
1733 mvneta_conf_mbus_windows(pp);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001734
Simon Glassd1998a92020-12-03 16:55:21 -07001735 /* PHY interface is already decoded in mvneta_of_to_plat() */
Stefan Roesee3b9c982015-11-19 07:46:15 +01001736 pp->phy_interface = pdata->phy_interface;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001737
Konstantin Porotchkin278d30c2017-02-16 13:52:28 +02001738 /* fetch 'fixed-link' property from 'neta' node */
1739 fl_node = fdt_subnode_offset(blob, node, "fixed-link");
1740 if (fl_node != -FDT_ERR_NOTFOUND) {
1741 /* set phy_addr to invalid value for fixed link */
1742 pp->phyaddr = PHY_MAX_ADDR + 1;
1743 pp->duplex = fdtdec_get_bool(blob, fl_node, "full-duplex");
1744 pp->speed = fdtdec_get_int(blob, fl_node, "speed", 0);
1745 } else {
1746 /* Now read phyaddr from DT */
1747 addr = fdtdec_get_int(blob, node, "phy", 0);
1748 addr = fdt_node_offset_by_phandle(blob, addr);
1749 pp->phyaddr = fdtdec_get_int(blob, addr, "reg", 0);
1750 }
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001751
Stefan Roesee3b9c982015-11-19 07:46:15 +01001752 bus = mdio_alloc();
1753 if (!bus) {
1754 printf("Failed to allocate MDIO bus\n");
1755 return -ENOMEM;
1756 }
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001757
Stefan Roesee3b9c982015-11-19 07:46:15 +01001758 bus->read = mvneta_mdio_read;
1759 bus->write = mvneta_mdio_write;
1760 snprintf(bus->name, sizeof(bus->name), dev->name);
1761 bus->priv = (void *)pp;
1762 pp->bus = bus;
1763
Konstantin Porotchkin976feda2017-02-16 13:52:27 +02001764 ret = mdio_register(bus);
1765 if (ret)
1766 return ret;
1767
Simon Glassbcee8d62019-12-06 21:41:35 -07001768#if CONFIG_IS_ENABLED(DM_GPIO)
Aditya Prayoga18bfc8f2018-12-05 00:39:23 +08001769 gpio_request_by_name(dev, "phy-reset-gpios", 0,
1770 &pp->phy_reset_gpio, GPIOD_IS_OUT);
1771
1772 if (dm_gpio_is_valid(&pp->phy_reset_gpio)) {
1773 dm_gpio_set_value(&pp->phy_reset_gpio, 1);
1774 mdelay(10);
1775 dm_gpio_set_value(&pp->phy_reset_gpio, 0);
1776 }
1777#endif
1778
Konstantin Porotchkin976feda2017-02-16 13:52:27 +02001779 return board_network_enable(bus);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001780}
Stefan Roesee3b9c982015-11-19 07:46:15 +01001781
1782static void mvneta_stop(struct udevice *dev)
1783{
1784 struct mvneta_port *pp = dev_get_priv(dev);
1785
1786 mvneta_port_down(pp);
1787 mvneta_port_disable(pp);
1788}
1789
1790static const struct eth_ops mvneta_ops = {
1791 .start = mvneta_start,
1792 .send = mvneta_send,
1793 .recv = mvneta_recv,
1794 .stop = mvneta_stop,
Matt Pelland0a85f022018-03-27 13:18:25 -04001795 .write_hwaddr = mvneta_write_hwaddr,
Stefan Roesee3b9c982015-11-19 07:46:15 +01001796};
1797
Simon Glassd1998a92020-12-03 16:55:21 -07001798static int mvneta_of_to_plat(struct udevice *dev)
Stefan Roesee3b9c982015-11-19 07:46:15 +01001799{
Simon Glassc69cda22020-12-03 16:55:20 -07001800 struct eth_pdata *pdata = dev_get_plat(dev);
Stefan Roesee3b9c982015-11-19 07:46:15 +01001801 const char *phy_mode;
1802
Masahiro Yamada25484932020-07-17 14:36:48 +09001803 pdata->iobase = dev_read_addr(dev);
Stefan Roesee3b9c982015-11-19 07:46:15 +01001804
1805 /* Get phy-mode / phy_interface from DT */
1806 pdata->phy_interface = -1;
Simon Glasse160f7d2017-01-17 16:52:55 -07001807 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
1808 NULL);
Stefan Roesee3b9c982015-11-19 07:46:15 +01001809 if (phy_mode)
1810 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
1811 if (pdata->phy_interface == -1) {
1812 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1813 return -EINVAL;
1814 }
1815
1816 return 0;
1817}
1818
1819static const struct udevice_id mvneta_ids[] = {
1820 { .compatible = "marvell,armada-370-neta" },
1821 { .compatible = "marvell,armada-xp-neta" },
Stefan Roese544eefe2016-05-19 17:46:36 +02001822 { .compatible = "marvell,armada-3700-neta" },
Stefan Roesee3b9c982015-11-19 07:46:15 +01001823 { }
1824};
1825
1826U_BOOT_DRIVER(mvneta) = {
1827 .name = "mvneta",
1828 .id = UCLASS_ETH,
1829 .of_match = mvneta_ids,
Simon Glassd1998a92020-12-03 16:55:21 -07001830 .of_to_plat = mvneta_of_to_plat,
Stefan Roesee3b9c982015-11-19 07:46:15 +01001831 .probe = mvneta_probe,
1832 .ops = &mvneta_ops,
Simon Glass41575d82020-12-03 16:55:17 -07001833 .priv_auto = sizeof(struct mvneta_port),
Simon Glasscaa4daa2020-12-03 16:55:18 -07001834 .plat_auto = sizeof(struct eth_pdata),
Stefan Roesee3b9c982015-11-19 07:46:15 +01001835};