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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Yusuke Goda1a2334a2008-03-05 14:30:02 +09002/*
3 * SH7780 PCI Controller (PCIC) for U-Boot.
4 * (C) Dustin McIntire (dustin@sensoria.com)
Nobuhiro Iwamatsuab8f4d42008-03-24 02:11:26 +09005 * (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Yusuke Goda1a2334a2008-03-05 14:30:02 +09006 * (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
Yusuke Goda1a2334a2008-03-05 14:30:02 +09007 */
8
9#include <common.h>
Simon Glassc05ed002020-05-10 11:40:11 -060010#include <linux/delay.h>
Yusuke Goda1a2334a2008-03-05 14:30:02 +090011
Yusuke Goda1a2334a2008-03-05 14:30:02 +090012#include <pci.h>
Nobuhiro Iwamatsub5d10a12008-09-18 19:34:36 +090013#include <asm/processor.h>
14#include <asm/pci.h>
15#include <asm/io.h>
Yusuke Goda1a2334a2008-03-05 14:30:02 +090016
17#define SH7780_VENDOR_ID 0x1912
18#define SH7780_DEVICE_ID 0x0002
19#define SH7780_PCICR_PREFIX 0xA5000000
20#define SH7780_PCICR_PFCS 0x00000800
21#define SH7780_PCICR_FTO 0x00000400
22#define SH7780_PCICR_PFE 0x00000200
23#define SH7780_PCICR_TBS 0x00000100
24#define SH7780_PCICR_ARBM 0x00000040
25#define SH7780_PCICR_IOCS 0x00000004
26#define SH7780_PCICR_PRST 0x00000002
27#define SH7780_PCICR_CFIN 0x00000001
28
Nobuhiro Iwamatsub5d10a12008-09-18 19:34:36 +090029#define p4_in(addr) (*(vu_long *)addr)
30#define p4_out(data, addr) (*(vu_long *)addr) = (data)
31#define p4_inw(addr) (*(vu_short *)addr)
32#define p4_outw(data, addr) (*(vu_short *)addr) = (data)
Yusuke Goda1a2334a2008-03-05 14:30:02 +090033
34int pci_sh4_read_config_dword(struct pci_controller *hose,
35 pci_dev_t dev, int offset, u32 *value)
36{
37 u32 par_data = 0x80000000 | dev;
38
39 p4_out(par_data | (offset & 0xfc), SH7780_PCIPAR);
40 *value = p4_in(SH7780_PCIPDR);
41
42 return 0;
43}
44
45int pci_sh4_write_config_dword(struct pci_controller *hose,
46 pci_dev_t dev, int offset, u32 value)
47{
48 u32 par_data = 0x80000000 | dev;
49
50 p4_out(par_data | (offset & 0xfc), SH7780_PCIPAR);
51 p4_out(value, SH7780_PCIPDR);
52 return 0;
53}
54
55int pci_sh7780_init(struct pci_controller *hose)
56{
57 p4_out(0x01, SH7780_PCIECR);
58
59 if (p4_inw(SH7780_PCIVID) != SH7780_VENDOR_ID
Nobuhiro Iwamatsub5d10a12008-09-18 19:34:36 +090060 && p4_inw(SH7780_PCIDID) != SH7780_DEVICE_ID) {
Yusuke Goda1a2334a2008-03-05 14:30:02 +090061 printf("PCI: Unknown PCI host bridge.\n");
Nobuhiro Iwamatsub5d10a12008-09-18 19:34:36 +090062 return -1;
Yusuke Goda1a2334a2008-03-05 14:30:02 +090063 }
64 printf("PCI: SH7780 PCI host bridge found.\n");
65
66 /* Toggle PCI reset pin */
67 p4_out((SH7780_PCICR_PREFIX | SH7780_PCICR_PRST), SH7780_PCICR);
68 udelay(100000);
69 p4_out(SH7780_PCICR_PREFIX, SH7780_PCICR);
70 p4_outw(0x0047, SH7780_PCICMD);
71
Yoshihiro Shimoda06b18162009-02-25 14:26:42 +090072 p4_out(CONFIG_SH7780_PCI_LSR, SH7780_PCILSR0);
73 p4_out(CONFIG_SH7780_PCI_LAR, SH7780_PCILAR0);
Yusuke Goda1a2334a2008-03-05 14:30:02 +090074 p4_out(0x00000000, SH7780_PCILSR1);
75 p4_out(0, SH7780_PCILAR1);
Yoshihiro Shimoda06b18162009-02-25 14:26:42 +090076 p4_out(CONFIG_SH7780_PCI_BAR, SH7780_PCIMBAR0);
Yusuke Goda1a2334a2008-03-05 14:30:02 +090077 p4_out(0x00000000, SH7780_PCIMBAR1);
78
79 p4_out(0xFD000000, SH7780_PCIMBR0);
80 p4_out(0x00FC0000, SH7780_PCIMBMR0);
81
82 /* if use Operand Cache then enable PCICSCR Soonp bits. */
83 p4_out(0x08000000, SH7780_PCICSAR0);
84 p4_out(0x0000001B, SH7780_PCICSCR0); /* Snoop bit :On */
85
86 p4_out((SH7780_PCICR_PREFIX | SH7780_PCICR_CFIN | SH7780_PCICR_ARBM
87 | SH7780_PCICR_FTO | SH7780_PCICR_PFCS | SH7780_PCICR_PFE),
88 SH7780_PCICR);
89
90 pci_sh4_init(hose);
91 return 0;
92}