Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Holger Brunck | 0f2b721 | 2012-03-21 13:42:46 +0100 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2012 |
| 4 | * Holger Brunck, Keymile GmbH Hannover, <holger.brunck@keymile.com> |
| 5 | * Christian Herzig, Keymile AG Switzerland, <christian.herzig@keymile.com> |
Holger Brunck | 0f2b721 | 2012-03-21 13:42:46 +0100 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef __CONFIG_H |
| 9 | #define __CONFIG_H |
| 10 | |
| 11 | /* KMBEC FPGA (PRIO) */ |
| 12 | #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 |
| 13 | #define CONFIG_SYS_KMBEC_FPGA_SIZE 64 |
| 14 | |
Mario Six | 5bc0543 | 2018-03-28 14:38:20 +0200 | [diff] [blame] | 15 | #define CONFIG_HOSTNAME "kmcoge5ne" |
Holger Brunck | 0f2b721 | 2012-03-21 13:42:46 +0100 | [diff] [blame] | 16 | #define CONFIG_KM_BOARD_NAME "kmcoge5ne" |
| 17 | #define CONFIG_KM_DEF_NETDEV "netdev=eth1\0" |
Holger Brunck | be7576f | 2013-01-21 03:55:23 +0000 | [diff] [blame] | 18 | #define CONFIG_NAND_ECC_BCH |
Holger Brunck | 0f2b721 | 2012-03-21 13:42:46 +0100 | [diff] [blame] | 19 | #define CONFIG_NAND_KMETER1 |
| 20 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 21 | #define NAND_MAX_CHIPS 1 |
| 22 | #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */ |
| 23 | |
| 24 | #define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" |
| 25 | #define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" |
Holger Brunck | 0f2b721 | 2012-03-21 13:42:46 +0100 | [diff] [blame] | 26 | |
| 27 | /* |
| 28 | * High Level Configuration Options |
| 29 | */ |
| 30 | #define CONFIG_QE /* Has QE */ |
Holger Brunck | 0f2b721 | 2012-03-21 13:42:46 +0100 | [diff] [blame] | 31 | |
Mario Six | fb1b099 | 2019-01-21 09:17:34 +0100 | [diff] [blame] | 32 | /* include common defines/options for all Keymile boards */ |
| 33 | #include "km/keymile-common.h" |
| 34 | #include "km/km-powerpc.h" |
| 35 | |
| 36 | /* |
| 37 | * System Clock Setup |
| 38 | */ |
| 39 | #define CONFIG_83XX_CLKIN 66000000 |
| 40 | #define CONFIG_SYS_CLK_FREQ 66000000 |
| 41 | #define CONFIG_83XX_PCICLK 66000000 |
| 42 | |
| 43 | /* |
Mario Six | fb1b099 | 2019-01-21 09:17:34 +0100 | [diff] [blame] | 44 | * DDR Setup |
| 45 | */ |
Mario Six | 8a81bfd | 2019-01-21 09:18:15 +0100 | [diff] [blame] | 46 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ |
Mario Six | fb1b099 | 2019-01-21 09:17:34 +0100 | [diff] [blame] | 47 | #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ |
| 48 | |
Mario Six | fb1b099 | 2019-01-21 09:17:34 +0100 | [diff] [blame] | 49 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ |
| 50 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) |
| 51 | |
| 52 | #define CFG_83XX_DDR_USES_CS0 |
| 53 | |
| 54 | /* |
| 55 | * Manually set up DDR parameters |
| 56 | */ |
| 57 | #define CONFIG_DDR_II |
| 58 | #define CONFIG_SYS_DDR_SIZE 2048 /* MB */ |
| 59 | |
| 60 | /* |
| 61 | * The reserved memory |
| 62 | */ |
| 63 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
| 64 | #define CONFIG_SYS_FLASH_BASE 0xF0000000 |
| 65 | |
| 66 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
| 67 | #define CONFIG_SYS_RAMBOOT |
| 68 | #endif |
| 69 | |
| 70 | /* Reserve 768 kB for Mon */ |
| 71 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
| 72 | |
| 73 | /* |
| 74 | * Initial RAM Base Address Setup |
| 75 | */ |
| 76 | #define CONFIG_SYS_INIT_RAM_LOCK |
| 77 | #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ |
| 78 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ |
| 79 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ |
| 80 | GENERATED_GBL_DATA_SIZE) |
| 81 | |
| 82 | /* |
| 83 | * Init Local Bus Memory Controller: |
| 84 | * |
| 85 | * Bank Bus Machine PortSz Size Device |
| 86 | * ---- --- ------- ------ ----- ------ |
| 87 | * 0 Local GPCM 16 bit 256MB FLASH |
| 88 | * 1 Local GPCM 8 bit 128MB GPIO/PIGGY |
| 89 | * |
| 90 | */ |
| 91 | /* |
| 92 | * FLASH on the Local Bus |
| 93 | */ |
| 94 | #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ |
| 95 | |
Mario Six | fb1b099 | 2019-01-21 09:17:34 +0100 | [diff] [blame] | 96 | |
| 97 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ |
| 98 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ |
| 99 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
| 100 | |
| 101 | /* |
| 102 | * PRIO1/PIGGY on the local bus CS1 |
| 103 | */ |
Mario Six | a8f9753 | 2019-01-21 09:18:01 +0100 | [diff] [blame] | 104 | |
Mario Six | fb1b099 | 2019-01-21 09:17:34 +0100 | [diff] [blame] | 105 | |
| 106 | /* |
| 107 | * Serial Port |
| 108 | */ |
| 109 | #define CONFIG_SYS_NS16550_SERIAL |
| 110 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 111 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
| 112 | |
| 113 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
| 114 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) |
| 115 | |
| 116 | /* |
| 117 | * QE UEC ethernet configuration |
| 118 | */ |
| 119 | #define CONFIG_UEC_ETH |
| 120 | #define CONFIG_ETHPRIME "UEC0" |
| 121 | |
Mario Six | fb1b099 | 2019-01-21 09:17:34 +0100 | [diff] [blame] | 122 | #define CONFIG_UEC_ETH1 /* GETH1 */ |
| 123 | #define UEC_VERBOSE_DEBUG 1 |
Mario Six | fb1b099 | 2019-01-21 09:17:34 +0100 | [diff] [blame] | 124 | |
| 125 | #ifdef CONFIG_UEC_ETH1 |
| 126 | #define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ |
| 127 | #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ |
| 128 | #define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 |
| 129 | #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH |
| 130 | #define CONFIG_SYS_UEC1_PHY_ADDR 0 |
| 131 | #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII |
| 132 | #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 |
| 133 | #endif |
| 134 | |
| 135 | /* |
| 136 | * Environment |
| 137 | */ |
| 138 | |
| 139 | #ifndef CONFIG_SYS_RAMBOOT |
| 140 | #ifndef CONFIG_ENV_ADDR |
| 141 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ |
| 142 | CONFIG_SYS_MONITOR_LEN) |
| 143 | #endif |
| 144 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
| 145 | #ifndef CONFIG_ENV_OFFSET |
| 146 | #define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) |
| 147 | #endif |
| 148 | |
| 149 | /* Address and size of Redundant Environment Sector */ |
| 150 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ |
| 151 | CONFIG_ENV_SECT_SIZE) |
| 152 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
| 153 | |
| 154 | #else /* CFG_SYS_RAMBOOT */ |
| 155 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
| 156 | #define CONFIG_ENV_SIZE 0x2000 |
| 157 | #endif /* CFG_SYS_RAMBOOT */ |
| 158 | |
| 159 | /* I2C */ |
| 160 | #define CONFIG_SYS_I2C |
| 161 | #define CONFIG_SYS_NUM_I2C_BUSES 4 |
| 162 | #define CONFIG_SYS_I2C_MAX_HOPS 1 |
| 163 | #define CONFIG_SYS_I2C_FSL |
| 164 | #define CONFIG_SYS_FSL_I2C_SPEED 200000 |
| 165 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
| 166 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 |
| 167 | #define CONFIG_SYS_I2C_OFFSET 0x3000 |
| 168 | #define CONFIG_SYS_FSL_I2C2_SPEED 200000 |
| 169 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F |
| 170 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 |
| 171 | #define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ |
| 172 | {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ |
| 173 | {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ |
| 174 | {1, {I2C_NULL_HOP} } } |
| 175 | |
| 176 | #define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ |
| 177 | |
| 178 | #if defined(CONFIG_CMD_NAND) |
| 179 | #define CONFIG_NAND_KMETER1 |
| 180 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 181 | #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE |
| 182 | #endif |
| 183 | |
| 184 | /* |
| 185 | * For booting Linux, the board info and command line data |
| 186 | * have to be in the first 8 MB of memory, since this is |
| 187 | * the maximum mapped by the Linux kernel during initialization. |
| 188 | */ |
| 189 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) |
| 190 | |
| 191 | /* |
Mario Six | fb1b099 | 2019-01-21 09:17:34 +0100 | [diff] [blame] | 192 | * Internal Definitions |
| 193 | */ |
| 194 | #define BOOTFLASH_START 0xF0000000 |
| 195 | |
| 196 | #define CONFIG_KM_CONSOLE_TTY "ttyS0" |
| 197 | |
| 198 | /* |
| 199 | * Environment Configuration |
| 200 | */ |
| 201 | #define CONFIG_ENV_OVERWRITE |
| 202 | #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ |
| 203 | #define CONFIG_KM_DEF_ENV "km-common=empty\0" |
| 204 | #endif |
| 205 | |
| 206 | #ifndef CONFIG_KM_DEF_ARCH |
| 207 | #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" |
| 208 | #endif |
| 209 | |
| 210 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 211 | CONFIG_KM_DEF_ENV \ |
| 212 | CONFIG_KM_DEF_ARCH \ |
| 213 | "newenv=" \ |
| 214 | "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ |
| 215 | "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ |
| 216 | "unlock=yes\0" \ |
| 217 | "" |
| 218 | |
| 219 | #if defined(CONFIG_UEC_ETH) |
| 220 | #define CONFIG_HAS_ETH0 |
| 221 | #endif |
Holger Brunck | 0f2b721 | 2012-03-21 13:42:46 +0100 | [diff] [blame] | 222 | |
| 223 | /* |
| 224 | * System IO Setup |
| 225 | */ |
| 226 | #define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI) |
| 227 | |
Holger Brunck | 0f2b721 | 2012-03-21 13:42:46 +0100 | [diff] [blame] | 228 | /** |
| 229 | * DDR RAM settings |
| 230 | */ |
| 231 | #define CONFIG_SYS_DDR_SDRAM_CFG (\ |
| 232 | SDRAM_CFG_SDRAM_TYPE_DDR2 | \ |
| 233 | SDRAM_CFG_SREN | \ |
| 234 | SDRAM_CFG_HSE) |
| 235 | |
| 236 | #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 |
| 237 | |
Holger Brunck | 0f2b721 | 2012-03-21 13:42:46 +0100 | [diff] [blame] | 238 | /** |
| 239 | * KMCOGE5NE has 512 MB RAM |
| 240 | */ |
| 241 | #define CONFIG_SYS_DDR_CS0_CONFIG (\ |
| 242 | CSCONFIG_EN | \ |
| 243 | CSCONFIG_AP | \ |
Valentin Longchamp | 22554ba | 2015-11-17 10:53:33 +0100 | [diff] [blame] | 244 | CSCONFIG_ODT_WR_ONLY_CURRENT | \ |
Holger Brunck | 0f2b721 | 2012-03-21 13:42:46 +0100 | [diff] [blame] | 245 | CSCONFIG_BANK_BIT_3 | \ |
| 246 | CSCONFIG_ROW_BIT_13 | \ |
| 247 | CSCONFIG_COL_BIT_10) |
Holger Brunck | 0f2b721 | 2012-03-21 13:42:46 +0100 | [diff] [blame] | 248 | |
| 249 | #define CONFIG_SYS_DDR_CLK_CNTL (\ |
| 250 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) |
| 251 | |
| 252 | #define CONFIG_SYS_DDR_INTERVAL (\ |
| 253 | (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ |
| 254 | (0x203 << SDRAM_INTERVAL_REFINT_SHIFT)) |
| 255 | |
| 256 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f |
| 257 | |
| 258 | #define CONFIG_SYS_DDRCDR (\ |
| 259 | DDRCDR_EN | \ |
| 260 | DDRCDR_Q_DRN) |
| 261 | #define CONFIG_SYS_DDR_MODE 0x47860452 |
| 262 | #define CONFIG_SYS_DDR_MODE2 0x8080c000 |
| 263 | |
| 264 | #define CONFIG_SYS_DDR_TIMING_0 (\ |
| 265 | (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ |
| 266 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ |
| 267 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ |
| 268 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ |
| 269 | (0 << TIMING_CFG0_WWT_SHIFT) | \ |
| 270 | (0 << TIMING_CFG0_RRT_SHIFT) | \ |
| 271 | (0 << TIMING_CFG0_WRT_SHIFT) | \ |
| 272 | (0 << TIMING_CFG0_RWT_SHIFT)) |
| 273 | |
| 274 | #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ |
| 275 | (2 << TIMING_CFG1_WRTORD_SHIFT) | \ |
| 276 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ |
| 277 | (3 << TIMING_CFG1_WRREC_SHIFT) | \ |
| 278 | (7 << TIMING_CFG1_REFREC_SHIFT) | \ |
| 279 | (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ |
| 280 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ |
| 281 | (3 << TIMING_CFG1_PRETOACT_SHIFT)) |
| 282 | |
| 283 | #define CONFIG_SYS_DDR_TIMING_2 (\ |
| 284 | (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \ |
| 285 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ |
| 286 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ |
| 287 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ |
| 288 | (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ |
| 289 | (5 << TIMING_CFG2_CPO_SHIFT) | \ |
| 290 | (0 << TIMING_CFG2_ADD_LAT_SHIFT)) |
| 291 | |
| 292 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
| 293 | |
| 294 | /* EEprom support */ |
| 295 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 |
| 296 | |
| 297 | /* |
Holger Brunck | 0f2b721 | 2012-03-21 13:42:46 +0100 | [diff] [blame] | 298 | * PAXE on the local bus CS3 |
| 299 | */ |
| 300 | #define CONFIG_SYS_PAXE_BASE 0xA0000000 |
| 301 | #define CONFIG_SYS_PAXE_SIZE 256 |
| 302 | |
Holger Brunck | 0f2b721 | 2012-03-21 13:42:46 +0100 | [diff] [blame] | 303 | |
Holger Brunck | 0f2b721 | 2012-03-21 13:42:46 +0100 | [diff] [blame] | 304 | /* |
| 305 | * BFTIC3 on the local bus CS4 |
| 306 | */ |
| 307 | #define CONFIG_SYS_BFTIC3_BASE 0xB0000000 |
| 308 | #define CONFIG_SYS_BFTIC3_SIZE 256 |
| 309 | |
Holger Brunck | 0f2b721 | 2012-03-21 13:42:46 +0100 | [diff] [blame] | 310 | |
Thomas Herzmann | 95209b6 | 2012-05-04 10:55:56 +0200 | [diff] [blame] | 311 | /* enable POST tests */ |
| 312 | #define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS) |
| 313 | #define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */ |
| 314 | #define CPM_POST_WORD_ADDR CONFIG_SYS_MEMTEST_END |
| 315 | #define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */ |
| 316 | #define CONFIG_TESTPIN_MASK 0x20 /* for kmcoge5ne */ |
Thomas Herzmann | 95209b6 | 2012-05-04 10:55:56 +0200 | [diff] [blame] | 317 | |
Holger Brunck | 0f2b721 | 2012-03-21 13:42:46 +0100 | [diff] [blame] | 318 | #endif /* CONFIG */ |