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wdenkcd0a9de2004-02-23 20:48:38 +00001/*
2 * (C) Copyright 2004
3 * Tolunay Orkun, Nextio Inc., torkun@nextio.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
wdenkcd0a9de2004-02-23 20:48:38 +000024#include <common.h>
wdenk4d13cba2004-03-14 14:09:05 +000025#include <asm/processor.h>
wdenkcd0a9de2004-02-23 20:48:38 +000026#include <i2c.h>
27#include <miiphy.h>
Stefan Roeseb36df562010-09-09 19:18:00 +020028#include <asm/ppc4xx-emac.h>
wdenkcd0a9de2004-02-23 20:48:38 +000029
Stefan Roesebbeff302008-06-02 17:37:28 +020030void sdram_init(void);
31
wdenkcd0a9de2004-02-23 20:48:38 +000032/*
33 * Configuration data for AMIS FS6377-01 Programmable 3-PLL Clock Generator
34 *
35 * CLKA output => Epson LCD Controller
36 * CLKB output => Not Connected
37 * CLKC output => Ethernet
38 * CLKD output => UART external clock
39 *
40 * Note: these values are obtained from device after init by micromonitor
41*/
42uchar pll_fs6377_regs[16] = {
43 0x28, 0xef, 0x53, 0x03, 0x4b, 0x80, 0x32, 0x80,
44 0x94, 0x32, 0x80, 0xd4, 0x56, 0xf6, 0xf6, 0xe0 };
45
46/*
47 * pll_init: Initialize AMIS IC FS6377-01 PLL
48 *
49 * PLL supplies Epson LCD Clock, Ethernet Clock and UART external clock
50 *
51 */
52int pll_init(void)
53{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020054 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
wdenkcd0a9de2004-02-23 20:48:38 +000055
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056 return i2c_write(CONFIG_SYS_I2C_PLL_ADDR, 0, 1,
wdenkcd0a9de2004-02-23 20:48:38 +000057 (uchar *) pll_fs6377_regs, sizeof(pll_fs6377_regs));
58}
59
60/*
wdenk4d13cba2004-03-14 14:09:05 +000061 * board_early_init_f: do early board initialization
wdenkcd0a9de2004-02-23 20:48:38 +000062 *
63 */
wdenk4d13cba2004-03-14 14:09:05 +000064int board_early_init_f(void)
wdenkcd0a9de2004-02-23 20:48:38 +000065{
66 /* initialize PLL so UART, LCD, Ethernet clocked at correctly */
67 (void) get_clocks();
68 pll_init();
69
70 /*-------------------------------------------------------------------------+
71 | Interrupt controller setup for the Walnut board.
72 | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
73 | IRQ 16 405GP internally generated; active low; level sensitive
74 | IRQ 17-24 RESERVED
75 | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
76 | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
77 | IRQ 27 (EXT IRQ 2) Not Used
78 | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
79 | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
80 | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
81 | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
82 | Note for Walnut board:
83 | An interrupt taken for the FPGA (IRQ 25) indicates that either
84 | the Mouse, Keyboard, IRDA, or External Expansion caused the
85 | interrupt. The FPGA must be read to determine which device
86 | caused the interrupt. The default setting of the FPGA clears
87 |
88 +-------------------------------------------------------------------------*/
89
Stefan Roese952e7762009-09-24 09:55:50 +020090 mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
91 mtdcr (UIC0ER, 0x00000000); /* disable all ints */
92 mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
93 mtdcr (UIC0PR, 0xFFFFFF83); /* set int polarities */
94 mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
95 mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
96 mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
wdenkcd0a9de2004-02-23 20:48:38 +000097
Stefan Roesed1c3b272009-09-09 16:25:29 +020098 mtebc (EBC0_CFG, 0xa8400000); /* EBC always driven */
wdenkcd0a9de2004-02-23 20:48:38 +000099
100 return 0; /* success */
101}
102
103/*
104 * checkboard: identify/verify the board we are running
105 *
106 * Remark: we just assume it is correct board here!
107 *
108 */
109int checkboard(void)
110{
111 printf("BOARD: Cogent CSB272\n");
112
113 return 0; /* success */
114}
115
116/*
117 * initram: Determine the size of mounted DRAM
118 *
119 * Size is determined by reading SDRAM configuration registers as
120 * configured by initialization code
121 *
122 */
Becky Bruce9973e3c2008-06-09 16:03:40 -0500123phys_size_t initdram (int board_type)
wdenkcd0a9de2004-02-23 20:48:38 +0000124{
125 ulong tot_size;
126 ulong bank_size;
127 ulong tmp;
128
Stefan Roesebbeff302008-06-02 17:37:28 +0200129 /*
130 * ToDo: Move the asm init routine sdram_init() to this C file,
131 * or even better use some common ppc4xx code available
Stefan Roesea47a12b2010-04-15 16:07:28 +0200132 * in arch/powerpc/cpu/ppc4xx
Stefan Roesebbeff302008-06-02 17:37:28 +0200133 */
134 sdram_init();
135
wdenkcd0a9de2004-02-23 20:48:38 +0000136 tot_size = 0;
137
Stefan Roese95b602b2009-09-24 13:59:57 +0200138 mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
Stefan Roesed1c3b272009-09-09 16:25:29 +0200139 tmp = mfdcr (SDRAM0_CFGDATA);
wdenkcd0a9de2004-02-23 20:48:38 +0000140 if (tmp & 0x00000001) {
141 bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
142 tot_size += bank_size;
143 }
144
Stefan Roese95b602b2009-09-24 13:59:57 +0200145 mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
Stefan Roesed1c3b272009-09-09 16:25:29 +0200146 tmp = mfdcr (SDRAM0_CFGDATA);
wdenkcd0a9de2004-02-23 20:48:38 +0000147 if (tmp & 0x00000001) {
148 bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
149 tot_size += bank_size;
150 }
151
Stefan Roese95b602b2009-09-24 13:59:57 +0200152 mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
Stefan Roesed1c3b272009-09-09 16:25:29 +0200153 tmp = mfdcr (SDRAM0_CFGDATA);
wdenkcd0a9de2004-02-23 20:48:38 +0000154 if (tmp & 0x00000001) {
155 bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
156 tot_size += bank_size;
157 }
158
Stefan Roese95b602b2009-09-24 13:59:57 +0200159 mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
Stefan Roesed1c3b272009-09-09 16:25:29 +0200160 tmp = mfdcr (SDRAM0_CFGDATA);
wdenkcd0a9de2004-02-23 20:48:38 +0000161 if (tmp & 0x00000001) {
162 bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
163 tot_size += bank_size;
164 }
165
166 return tot_size;
167}
168
169/*
170 * last_stage_init: final configurations (such as PHY etc)
171 *
172 */
173int last_stage_init(void)
174{
175 /* initialize the PHY */
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200176 miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR);
177
178 /* AUTO neg */
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500179 miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_BMCR,
180 BMCR_ANENABLE | BMCR_ANRESTART);
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200181
182 /* LEDs */
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500183 miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_NWAYTEST, 0x0d08);
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200184
wdenkcd0a9de2004-02-23 20:48:38 +0000185
186 return 0; /* success */
187}