blob: 73c44102c4442551b942805e65f23e45a2e0ab74 [file] [log] [blame]
York Sunf749db32014-06-23 15:15:56 -07001/*
2 * Copyright 2014 Freescale Semiconductor
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6#include <common.h>
7#include <malloc.h>
8#include <errno.h>
9#include <netdev.h>
10#include <fsl_ifc.h>
11#include <fsl_ddr.h>
12#include <asm/io.h>
13#include <fdt_support.h>
14#include <libfdt.h>
Bhupesh Sharma422cb082015-03-19 09:20:43 -070015#include <fsl_debug_server.h>
J. German Rivera7b3bd9a2015-01-06 13:19:02 -080016#include <fsl-mc/fsl_mc.h>
Prabhakar Kushwaha1b357212014-07-14 17:15:44 +053017#include <environment.h>
Scott Woodb991b982015-03-20 19:28:12 -070018#include <asm/arch-fsl-lsch3/soc.h>
York Sunf749db32014-06-23 15:15:56 -070019
20DECLARE_GLOBAL_DATA_PTR;
21
22int board_init(void)
23{
24 init_final_memctl_regs();
Prabhakar Kushwaha1b357212014-07-14 17:15:44 +053025
26#ifdef CONFIG_ENV_IS_NOWHERE
27 gd->env_addr = (ulong)&default_environment[0];
28#endif
29
York Sunf749db32014-06-23 15:15:56 -070030 return 0;
31}
32
33int board_early_init_f(void)
34{
Scott Woodb991b982015-03-20 19:28:12 -070035 fsl_lsch3_early_init_f();
York Sunf749db32014-06-23 15:15:56 -070036 return 0;
37}
38
York Sund9c68b12014-08-13 10:21:05 -070039void detail_board_ddr_info(void)
40{
41 puts("\nDDR ");
42 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
43 print_ddr_info(0);
44 if (gd->bd->bi_dram[2].size) {
45 puts("\nDP-DDR ");
46 print_size(gd->bd->bi_dram[2].size, "");
47 print_ddr_info(CONFIG_DP_DDR_CTRL);
48 }
49}
50
York Sunf749db32014-06-23 15:15:56 -070051int dram_init(void)
52{
York Sunf749db32014-06-23 15:15:56 -070053 gd->ram_size = initdram(0);
54
55 return 0;
56}
57
Bhupesh Sharma422cb082015-03-19 09:20:43 -070058#if defined(CONFIG_ARCH_MISC_INIT)
59int arch_misc_init(void)
60{
61#ifdef CONFIG_FSL_DEBUG_SERVER
62 debug_server_init();
63#endif
64
65 return 0;
66}
67#endif
68
69unsigned long get_dram_size_to_hide(void)
70{
71 unsigned long dram_to_hide = 0;
72
73/* Carve the Debug Server private DRAM block from the end of DRAM */
74#ifdef CONFIG_FSL_DEBUG_SERVER
75 dram_to_hide += debug_server_get_dram_block_size();
76#endif
77
78/* Carve the MC private DRAM block from the end of DRAM */
79#ifdef CONFIG_FSL_MC_ENET
80 dram_to_hide += mc_get_dram_block_size();
81#endif
82
Prabhakar Kushwaha5c055082015-06-02 10:55:52 +053083 return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN);
Bhupesh Sharma422cb082015-03-19 09:20:43 -070084}
85
York Sunf749db32014-06-23 15:15:56 -070086int board_eth_init(bd_t *bis)
87{
88 int error = 0;
89
90#ifdef CONFIG_SMC91111
91 error = smc91111_initialize(0, CONFIG_SMC91111_BASE);
92#endif
93
94#ifdef CONFIG_FSL_MC_ENET
95 error = cpu_eth_init(bis);
96#endif
97 return error;
98}
99
100#ifdef CONFIG_FSL_MC_ENET
101void fdt_fixup_board_enet(void *fdt)
102{
103 int offset;
104
J. German Rivera7b3bd9a2015-01-06 13:19:02 -0800105 offset = fdt_path_offset(fdt, "/fsl-mc");
106
107 /*
108 * TODO: Remove this when backward compatibility
109 * with old DT node (fsl,dprc@0) is no longer needed.
110 */
111 if (offset < 0)
112 offset = fdt_path_offset(fdt, "/fsl,dprc@0");
113
114 if (offset < 0) {
115 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
116 __func__, offset);
117 return;
118 }
119
York Sunf749db32014-06-23 15:15:56 -0700120 if (get_mc_boot_status() == 0)
121 fdt_status_okay(fdt, offset);
122 else
123 fdt_status_fail(fdt, offset);
124}
125#endif
126
127#ifdef CONFIG_OF_BOARD_SETUP
Simon Glasse895a4b2014-10-23 18:58:47 -0600128int ft_board_setup(void *blob, bd_t *bd)
York Sunf749db32014-06-23 15:15:56 -0700129{
Bhupesh Sharmaa2dc8182015-05-28 14:54:10 +0530130 u64 base[CONFIG_NR_DRAM_BANKS];
131 u64 size[CONFIG_NR_DRAM_BANKS];
York Sunf749db32014-06-23 15:15:56 -0700132
York Sun8bfa3012014-09-08 12:20:01 -0700133 ft_cpu_setup(blob, bd);
134
Bhupesh Sharmaa2dc8182015-05-28 14:54:10 +0530135 /* fixup DT for the two GPP DDR banks */
136 base[0] = gd->bd->bi_dram[0].start;
137 size[0] = gd->bd->bi_dram[0].size;
138 base[1] = gd->bd->bi_dram[1].start;
139 size[1] = gd->bd->bi_dram[1].size;
140
141 fdt_fixup_memory_banks(blob, base, size, 2);
York Sunf749db32014-06-23 15:15:56 -0700142
143#ifdef CONFIG_FSL_MC_ENET
144 fdt_fixup_board_enet(blob);
Prabhakar Kushwahaa2a55e52015-03-19 09:20:45 -0700145 fsl_mc_ldpaa_exit(bd);
York Sunf749db32014-06-23 15:15:56 -0700146#endif
Simon Glasse895a4b2014-10-23 18:58:47 -0600147
148 return 0;
York Sunf749db32014-06-23 15:15:56 -0700149}
150#endif