blob: 9009afa3ad890625346b7046b370ce789b9bc8a6 [file] [log] [blame]
Priyanka Jain062ef1a2013-10-18 17:19:06 +05301/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <i2c.h>
9#include <hwconfig.h>
10#include <asm/mmu.h>
York Sun5614e712013-09-30 09:22:09 -070011#include <fsl_ddr_sdram.h>
12#include <fsl_ddr_dimm_params.h>
Priyanka Jain062ef1a2013-10-18 17:19:06 +053013#include <asm/fsl_law.h>
14#include "ddr.h"
15
16DECLARE_GLOBAL_DATA_PTR;
17
18int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
19 unsigned int controller_number,
20 unsigned int dimm_number)
21{
22 const char dimm_model[] = "RAW timing DDR";
23
24 if ((controller_number == 0) && (dimm_number == 0)) {
25 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
26 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
27 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
28 }
29
30 return 0;
31}
32
33void fsl_ddr_board_options(memctl_options_t *popts,
34 dimm_params_t *pdimm,
35 unsigned int ctrl_num)
36{
37 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
38 ulong ddr_freq;
39
40 if (ctrl_num > 1) {
41 printf("Not supported controller number %d\n", ctrl_num);
42 return;
43 }
44 if (!pdimm->n_ranks)
45 return;
46
47 pbsp = udimms[0];
48
49 /* Get clk_adjust, cpo, write_data_delay,2t, according to the board ddr
50 * freqency and n_banks specified in board_specific_parameters table.
51 */
52 ddr_freq = get_ddr_freq(0) / 1000000;
53 while (pbsp->datarate_mhz_high) {
54 if (pbsp->n_ranks == pdimm->n_ranks &&
55 (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
56 if (ddr_freq <= pbsp->datarate_mhz_high) {
57 popts->cpo_override = pbsp->cpo;
58 popts->write_data_delay =
59 pbsp->write_data_delay;
60 popts->clk_adjust = pbsp->clk_adjust;
61 popts->wrlvl_start = pbsp->wrlvl_start;
62 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
63 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
64 popts->twot_en = pbsp->force_2t;
65 goto found;
66 }
67 pbsp_highest = pbsp;
68 }
69 pbsp++;
70 }
71
72 if (pbsp_highest) {
73 printf("Error: board specific timing not found\n");
74 printf("for data rate %lu MT/s\n", ddr_freq);
75 printf("Trying to use the highest speed (%u) parameters\n",
76 pbsp_highest->datarate_mhz_high);
77 popts->cpo_override = pbsp_highest->cpo;
78 popts->write_data_delay = pbsp_highest->write_data_delay;
79 popts->clk_adjust = pbsp_highest->clk_adjust;
80 popts->wrlvl_start = pbsp_highest->wrlvl_start;
81 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
82 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
83 popts->twot_en = pbsp_highest->force_2t;
84 } else {
85 panic("DIMM is not supported by this board");
86 }
87found:
88 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
89 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
90 "wrlvl_ctrl_3 0x%x\n",
91 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
92 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
93 pbsp->wrlvl_ctl_3);
94
95 /*
96 * Factors to consider for half-strength driver enable:
97 * - number of DIMMs installed
98 */
99 popts->half_strength_driver_enable = 0;
100 /*
101 * Write leveling override
102 */
103 popts->wrlvl_override = 1;
104 popts->wrlvl_sample = 0xf;
105
106 /*
107 * rtt and rtt_wr override
108 */
109 popts->rtt_override = 0;
110
111 /* Enable ZQ calibration */
112 popts->zq_en = 1;
113
114 /* DHC_EN =1, ODT = 75 Ohm */
115 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
116 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
117}
118
119phys_size_t initdram(int board_type)
120{
121 phys_size_t dram_size;
122
123 puts("Initializing....using SPD\n");
124
125 dram_size = fsl_ddr_sdram();
126
127 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
128 dram_size *= 0x100000;
129
130 puts(" DDR: ");
131 return dram_size;
132}