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Kumar Gala3b558e22008-01-17 02:02:10 -06001/*
2 * Copyright 2008 Freescale Semiconductor, Inc.
3 *
4 * (C) Copyright 2000
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <common.h>
27#include <asm/mmu.h>
28
29struct fsl_e_tlb_entry tlb_table[] = {
30 /* TLB 0 - for temp stack in cache */
31 SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
32 MAS3_SX|MAS3_SW|MAS3_SR, 0,
33 0, 0, BOOKE_PAGESZ_4K, 0),
34 SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
35 MAS3_SX|MAS3_SW|MAS3_SR, 0,
36 0, 0, BOOKE_PAGESZ_4K, 0),
37 SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
38 MAS3_SX|MAS3_SW|MAS3_SR, 0,
39 0, 0, BOOKE_PAGESZ_4K, 0),
40 SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
41 MAS3_SX|MAS3_SW|MAS3_SR, 0,
42 0, 0, BOOKE_PAGESZ_4K, 0),
43
44
45 /*
46 * TLB 0, 1: 128M Non-cacheable, guarded
47 * 0xf8000000 128M FLASH
48 * Out of reset this entry is only 4K.
49 */
50 SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
51 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
52 0, 1, BOOKE_PAGESZ_64M, 1),
53 SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x4000000, CFG_FLASH_BASE + 0x4000000,
54 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
55 0, 0, BOOKE_PAGESZ_64M, 1),
56
57 /*
58 * TLB 2: 256M Non-cacheable, guarded
59 * 0x80000000 256M PCI1 MEM First half
60 */
61 SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
62 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
63 0, 2, BOOKE_PAGESZ_256M, 1),
64
65 /*
66 * TLB 3: 256M Non-cacheable, guarded
67 * 0x90000000 256M PCI1 MEM Second half
68 */
69 SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000,
70 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
71 0, 3, BOOKE_PAGESZ_256M, 1),
72
73 /*
74 * TLB 4: 256M Non-cacheable, guarded
75 * 0xc0000000 256M Rapid IO MEM First half
76 */
77 SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
78 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
79 0, 4, BOOKE_PAGESZ_256M, 1),
80
81 /*
82 * TLB 5: 256M Non-cacheable, guarded
83 * 0xd0000000 256M Rapid IO MEM Second half
84 */
85 SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000,
86 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
87 0, 5, BOOKE_PAGESZ_256M, 1),
88
89 /*
90 * TLB 6: 64M Non-cacheable, guarded
91 * 0xe000_0000 1M CCSRBAR
92 * 0xe200_0000 16M PCI1 IO
93 */
94 SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR,
95 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
96 0, 6, BOOKE_PAGESZ_64M, 1),
97
98 /*
99 * TLB 7+8: 512M DDR, cache disabled (needed for memory test)
100 * 0x00000000 512M DDR System memory
101 * Without SPD EEPROM configured DDR, this must be setup manually.
102 * Make sure the TLB count at the top of this table is correct.
103 * Likely it needs to be increased by two for these entries.
104 */
105 SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
106 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
107 0, 7, BOOKE_PAGESZ_256M, 1),
108
109 SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x10000000, CFG_DDR_SDRAM_BASE + 0x10000000,
110 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
111 0, 8, BOOKE_PAGESZ_256M, 1),
112};
113
114int num_tlb_entries = ARRAY_SIZE(tlb_table);