blob: aa92fc4281056802bd4a11b8c53605759c94b4a1 [file] [log] [blame]
wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001
3 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkc6097192002-11-03 00:24:07 +00006 */
7
8#include <common.h>
9#include <mpc824x.h>
10#include <pci.h>
Ben Warren8ca0b3f2008-08-31 10:45:44 -070011#include <netdev.h>
wdenkc6097192002-11-03 00:24:07 +000012
13int checkboard (void)
14{
15 ulong busfreq = get_bus_freq(0);
16 char buf[32];
17
18 printf("Board: MUSENKI Local Bus at %s MHz\n", strmhz(buf, busfreq));
19 return 0;
20
21}
22
Wolfgang Denk53677ef2008-05-20 16:00:29 +020023#if 0 /* NOT USED */
wdenkc6097192002-11-03 00:24:07 +000024int checkflash (void)
25{
26 /* TODO: XXX XXX XXX */
27 printf ("## Test not implemented yet ##\n");
28
29 return (0);
30}
31#endif
32
Becky Bruce9973e3c2008-06-09 16:03:40 -050033phys_size_t initdram (int board_type)
wdenkc6097192002-11-03 00:24:07 +000034{
wdenkc83bf6a2004-01-06 22:38:14 +000035 long size;
36 long new_bank0_end;
37 long mear1;
38 long emear1;
wdenkc6097192002-11-03 00:24:07 +000039
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020040 size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
wdenkc6097192002-11-03 00:24:07 +000041
wdenkc83bf6a2004-01-06 22:38:14 +000042 new_bank0_end = size - 1;
43 mear1 = mpc824x_mpc107_getreg(MEAR1);
44 emear1 = mpc824x_mpc107_getreg(EMEAR1);
45 mear1 = (mear1 & 0xFFFFFF00) |
46 ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
47 emear1 = (emear1 & 0xFFFFFF00) |
48 ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
49 mpc824x_mpc107_setreg(MEAR1, mear1);
50 mpc824x_mpc107_setreg(EMEAR1, emear1);
wdenkc6097192002-11-03 00:24:07 +000051
wdenkc83bf6a2004-01-06 22:38:14 +000052 return (size);
wdenkc6097192002-11-03 00:24:07 +000053}
54
55/*
56 * Initialize PCI Devices
57 */
58#ifndef CONFIG_PCI_PNP
59static struct pci_config_table pci_sandpoint_config_table[] = {
60#if 0
61 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
62 0x0, 0x0, 0x0, /* unknown eth0 divice */
63 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
64 PCI_ENET0_MEMADDR,
65 PCI_COMMAND_IO |
66 PCI_COMMAND_MEMORY |
67 PCI_COMMAND_MASTER }},
68 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
69 0x0, 0x0, 0x0, /* unknown eth1 device */
70 pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
71 PCI_ENET1_MEMADDR,
72 PCI_COMMAND_IO |
73 PCI_COMMAND_MEMORY |
74 PCI_COMMAND_MASTER }},
75#endif
76 { }
77};
78#endif
79
80struct pci_controller hose = {
81#ifndef CONFIG_PCI_PNP
82 config_table: pci_sandpoint_config_table,
83#endif
84};
85
stroesead10dd92003-02-14 11:21:23 +000086void pci_init_board(void)
wdenkc6097192002-11-03 00:24:07 +000087{
88 pci_mpc824x_init(&hose);
89}
Ben Warren8ca0b3f2008-08-31 10:45:44 -070090
91int board_eth_init(bd_t *bis)
92{
93 return pci_eth_init(bis);
94}