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Haiying Wang765547d2009-03-27 17:02:45 -04001/*
Kumar Galae5fe96b2011-01-04 18:04:01 -06002 * Copyright 2009-2011 Freescale Semiconductor, Inc.
Haiying Wang765547d2009-03-27 17:02:45 -04003 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02004 * SPDX-License-Identifier: GPL-2.0+
Haiying Wang765547d2009-03-27 17:02:45 -04005 */
6
7/*
8 * mpc8569mds board configuration file
9 */
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13/* High Level Configuration Options */
14#define CONFIG_BOOKE 1 /* BOOKE */
15#define CONFIG_E500 1 /* BOOKE e500 family */
16#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */
17#define CONFIG_MPC8569 1 /* MPC8569 specific */
18#define CONFIG_MPC8569MDS 1 /* MPC8569MDS board specific */
19
20#define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */
21
Kumar Galae5fe96b2011-01-04 18:04:01 -060022#define CONFIG_SYS_SRIO
23#define CONFIG_SRIO1 /* SRIO port 1 */
24
Haiying Wang765547d2009-03-27 17:02:45 -040025#define CONFIG_PCI 1 /* Disable PCI/PCIE */
26#define CONFIG_PCIE1 1 /* PCIE controller */
27#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
Gabor Juhos842033e2013-05-30 07:06:12 +000028#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
Haiying Wang765547d2009-03-27 17:02:45 -040029#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
30#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
31#define CONFIG_QE /* Enable QE */
32#define CONFIG_ENV_OVERWRITE
33#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
34
Haiying Wang765547d2009-03-27 17:02:45 -040035#ifndef __ASSEMBLY__
36extern unsigned long get_clock_freq(void);
37#endif
38/* Replace a call to get_clock_freq (after it is implemented)*/
Dave Liu67351042009-05-18 17:49:23 +080039#define CONFIG_SYS_CLK_FREQ 66666666
40#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
Haiying Wang765547d2009-03-27 17:02:45 -040041
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020042#ifdef CONFIG_ATM
Liu Yuc95d5412009-11-27 15:31:52 +080043#define CONFIG_PQ_MDS_PIB
44#define CONFIG_PQ_MDS_PIB_ATM
45#endif
46
Haiying Wang765547d2009-03-27 17:02:45 -040047/*
48 * These can be toggled for performance analysis, otherwise use default.
49 */
50#define CONFIG_L2_CACHE /* toggle L2 cache */
51#define CONFIG_BTB /* toggle branch predition */
52
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020053#ifdef CONFIG_NAND
Liu Yu674ef7b2010-01-18 19:03:28 +080054#define CONFIG_NAND_U_BOOT 1
55#define CONFIG_RAMBOOT_NAND 1
Haiying Wang96196a12010-11-10 15:37:13 -050056#ifdef CONFIG_NAND_SPL
57#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
58#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
59#else
Kumar Gala00203c62011-01-31 15:57:01 -060060#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
Wolfgang Denk2ae18242010-10-06 09:05:45 +020061#define CONFIG_SYS_TEXT_BASE 0xf8f82000
62#endif
Haiying Wang96196a12010-11-10 15:37:13 -050063#endif
Wolfgang Denk2ae18242010-10-06 09:05:45 +020064
65#ifndef CONFIG_SYS_TEXT_BASE
66#define CONFIG_SYS_TEXT_BASE 0xfff80000
Liu Yu674ef7b2010-01-18 19:03:28 +080067#endif
68
Haiying Wang96196a12010-11-10 15:37:13 -050069#ifndef CONFIG_SYS_MONITOR_BASE
70#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
71#endif
72
Haiying Wang765547d2009-03-27 17:02:45 -040073/*
74 * Only possible on E500 Version 2 or newer cores.
75 */
76#define CONFIG_ENABLE_36BIT_PHYS 1
77
78#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
Haiying Wang3aed5502010-09-29 13:31:35 -040079#define CONFIG_BOARD_EARLY_INIT_R 1
Anton Vorontsov7f52ed52009-10-15 17:47:06 +040080#define CONFIG_HWCONFIG
Haiying Wang765547d2009-03-27 17:02:45 -040081
82#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
83#define CONFIG_SYS_MEMTEST_END 0x00400000
84
85/*
Liu Yu674ef7b2010-01-18 19:03:28 +080086 * Config the L2 Cache as L2 SRAM
87 */
88#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
89#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
90#define CONFIG_SYS_L2_SIZE (512 << 10)
91#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
92
Timur Tabie46fedf2011-08-04 18:03:41 -050093#define CONFIG_SYS_CCSRBAR 0xe0000000
94#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Haiying Wang765547d2009-03-27 17:02:45 -040095
Kumar Gala8d22ddc2011-11-09 09:10:49 -060096#if defined(CONFIG_NAND_SPL)
Timur Tabie46fedf2011-08-04 18:03:41 -050097#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
Liu Yu674ef7b2010-01-18 19:03:28 +080098#endif
99
Haiying Wang765547d2009-03-27 17:02:45 -0400100/* DDR Setup */
York Sun5614e712013-09-30 09:22:09 -0700101#define CONFIG_SYS_FSL_DDR3
Haiying Wang765547d2009-03-27 17:02:45 -0400102#undef CONFIG_FSL_DDR_INTERACTIVE
103#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
104#define CONFIG_DDR_SPD
Haiying Wang765547d2009-03-27 17:02:45 -0400105#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
106
107#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
108
109#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
110 /* DDR is system memory*/
111#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
112
113#define CONFIG_NUM_DDR_CONTROLLERS 1
114#define CONFIG_DIMM_SLOTS_PER_CTLR 1
115#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
116
117/* I2C addresses of SPD EEPROMs */
Kumar Galac39f44d2011-01-31 22:18:47 -0600118#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
Haiying Wang765547d2009-03-27 17:02:45 -0400119
120/* These are used when DDR doesn't use SPD. */
121#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */
122#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
123#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
124#define CONFIG_SYS_DDR_TIMING_3 0x00020000
125#define CONFIG_SYS_DDR_TIMING_0 0x00330004
126#define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644
127#define CONFIG_SYS_DDR_TIMING_2 0x002888D0
128#define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000
129#define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040
130#define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521
131#define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000
132#define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000
133#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
134#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000
135#define CONFIG_SYS_DDR_TIMING_4 0x00220001
136#define CONFIG_SYS_DDR_TIMING_5 0x03402400
137#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
138#define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604
139#define CONFIG_SYS_DDR_CDR_1 0x80040000
140#define CONFIG_SYS_DDR_CDR_2 0x00000000
141#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
142#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
143#define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */
144#define CONFIG_SYS_DDR_CONTROL2 0x24400000
145
146#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
147#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
148#define CONFIG_SYS_DDR_SBE 0x00010000
149
150#undef CONFIG_CLOCKS_IN_MHZ
151
152/*
153 * Local Bus Definitions
154 */
155
156#define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */
157#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
158
159#define CONFIG_SYS_BCSR_BASE 0xf8000000
160#define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE
161
162/*Chip select 0 - Flash*/
Liu Yu674ef7b2010-01-18 19:03:28 +0800163#define CONFIG_FLASH_BR_PRELIM 0xfe000801
164#define CONFIG_FLASH_OR_PRELIM 0xfe000ff7
Haiying Wang765547d2009-03-27 17:02:45 -0400165
Haiying Wang399b53c2009-05-20 12:30:32 -0400166/*Chip select 1 - BCSR*/
Haiying Wang765547d2009-03-27 17:02:45 -0400167#define CONFIG_SYS_BR1_PRELIM 0xf8000801
168#define CONFIG_SYS_OR1_PRELIM 0xffffe9f7
169
Haiying Wang399b53c2009-05-20 12:30:32 -0400170/*Chip select 4 - PIB*/
171#define CONFIG_SYS_BR4_PRELIM 0xf8008801
172#define CONFIG_SYS_OR4_PRELIM 0xffffe9f7
173
174/*Chip select 5 - PIB*/
175#define CONFIG_SYS_BR5_PRELIM 0xf8010801
176#define CONFIG_SYS_OR5_PRELIM 0xffffe9f7
177
Haiying Wang765547d2009-03-27 17:02:45 -0400178#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
179#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
180#undef CONFIG_SYS_FLASH_CHECKSUM
181#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
182#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
183
Kumar Galaa55bb832010-11-29 14:32:11 -0600184#if defined(CONFIG_RAMBOOT_NAND)
Liu Yu674ef7b2010-01-18 19:03:28 +0800185#define CONFIG_SYS_RAMBOOT
Kumar Galaa55bb832010-11-29 14:32:11 -0600186#define CONFIG_SYS_EXTRA_ENV_RELOC
Liu Yu674ef7b2010-01-18 19:03:28 +0800187#else
188#undef CONFIG_SYS_RAMBOOT
189#endif
190
Haiying Wang765547d2009-03-27 17:02:45 -0400191#define CONFIG_FLASH_CFI_DRIVER
192#define CONFIG_SYS_FLASH_CFI
193#define CONFIG_SYS_FLASH_EMPTY_INFO
194
Anton Vorontsova29155e2009-10-15 17:47:08 +0400195/* Chip select 3 - NAND */
Liu Yu674ef7b2010-01-18 19:03:28 +0800196#ifndef CONFIG_NAND_SPL
Anton Vorontsova29155e2009-10-15 17:47:08 +0400197#define CONFIG_SYS_NAND_BASE 0xFC000000
Liu Yu674ef7b2010-01-18 19:03:28 +0800198#else
199#define CONFIG_SYS_NAND_BASE 0xFFF00000
200#endif
201
202/* NAND boot: 4K NAND loader config */
203#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
204#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
205#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
206#define CONFIG_SYS_NAND_U_BOOT_START \
207 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
208#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
209#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
210#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
211
Anton Vorontsova29155e2009-10-15 17:47:08 +0400212#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
213#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, }
214#define CONFIG_SYS_MAX_NAND_DEVICE 1
215#define CONFIG_MTD_NAND_VERIFY_WRITE 1
216#define CONFIG_CMD_NAND 1
217#define CONFIG_NAND_FSL_ELBC 1
218#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
Matthew McClintocka3055c52011-04-05 14:39:33 -0500219#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
Anton Vorontsova29155e2009-10-15 17:47:08 +0400220 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
221 | BR_PS_8 /* Port Size = 8 bit */ \
222 | BR_MS_FCM /* MSEL = FCM */ \
223 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500224#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
Anton Vorontsova29155e2009-10-15 17:47:08 +0400225 | OR_FCM_CSCT \
226 | OR_FCM_CST \
227 | OR_FCM_CHT \
228 | OR_FCM_SCY_1 \
229 | OR_FCM_TRLX \
230 | OR_FCM_EHTR)
Liu Yu674ef7b2010-01-18 19:03:28 +0800231
232#ifdef CONFIG_RAMBOOT_NAND
Matthew McClintocka3055c52011-04-05 14:39:33 -0500233#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
234#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM/* NAND Options */
Liu Yu674ef7b2010-01-18 19:03:28 +0800235#define CONFIG_SYS_BR3_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
236#define CONFIG_SYS_OR3_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
237#else
238#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
239#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500240#define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
241#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Liu Yu674ef7b2010-01-18 19:03:28 +0800242#endif
Haiying Wang765547d2009-03-27 17:02:45 -0400243
Haiying Wang765547d2009-03-27 17:02:45 -0400244#define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */
245#define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */
246#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
247#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
248
249#define CONFIG_SYS_INIT_RAM_LOCK 1
250#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200251#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
Haiying Wang765547d2009-03-27 17:02:45 -0400252
Haiying Wang765547d2009-03-27 17:02:45 -0400253#define CONFIG_SYS_GBL_DATA_OFFSET \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200254 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Haiying Wang765547d2009-03-27 17:02:45 -0400255#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
256
257#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
Haiying Wangfb279492009-06-04 16:12:39 -0400258#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
Haiying Wang765547d2009-03-27 17:02:45 -0400259
260/* Serial Port */
261#define CONFIG_CONS_INDEX 1
Haiying Wang765547d2009-03-27 17:02:45 -0400262#define CONFIG_SYS_NS16550
263#define CONFIG_SYS_NS16550_SERIAL
264#define CONFIG_SYS_NS16550_REG_SIZE 1
265#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Kumar Gala93341902010-04-07 01:34:11 -0500266#ifdef CONFIG_NAND_SPL
267#define CONFIG_NS16550_MIN_FUNCTIONS
268#endif
Haiying Wang765547d2009-03-27 17:02:45 -0400269
270#define CONFIG_SYS_BAUDRATE_TABLE \
271 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
272
273#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
274#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
275
276/* Use the HUSH parser*/
277#define CONFIG_SYS_HUSH_PARSER
278#ifdef CONFIG_SYS_HUSH_PARSER
Haiying Wang765547d2009-03-27 17:02:45 -0400279#endif
280
281/* pass open firmware flat tree */
282#define CONFIG_OF_LIBFDT 1
283#define CONFIG_OF_BOARD_SETUP 1
284#define CONFIG_OF_STDOUT_VIA_ALIAS 1
285
Haiying Wang765547d2009-03-27 17:02:45 -0400286/*
287 * I2C
288 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200289#define CONFIG_SYS_I2C
290#define CONFIG_SYS_I2C_FSL
291#define CONFIG_SYS_FSL_I2C_SPEED 400000
292#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
293#define CONFIG_SYS_FSL_I2C2_SPEED 400000
294#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
295#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
296#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
297#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
Haiying Wang765547d2009-03-27 17:02:45 -0400298
299/*
300 * I2C2 EEPROM
301 */
302#define CONFIG_ID_EEPROM
303#ifdef CONFIG_ID_EEPROM
304#define CONFIG_SYS_I2C_EEPROM_NXID
305#endif
306#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
307#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
308#define CONFIG_SYS_EEPROM_BUS_NUM 1
309
310#define PLPPAR1_I2C_BIT_MASK 0x0000000F
311#define PLPPAR1_I2C2_VAL 0x00000000
Anton Vorontsov7f52ed52009-10-15 17:47:06 +0400312#define PLPPAR1_ESDHC_VAL 0x0000000A
Haiying Wang765547d2009-03-27 17:02:45 -0400313#define PLPDIR1_I2C_BIT_MASK 0x0000000F
314#define PLPDIR1_I2C2_VAL 0x0000000F
Anton Vorontsov7f52ed52009-10-15 17:47:06 +0400315#define PLPDIR1_ESDHC_VAL 0x00000006
Anton Vorontsovc4ca10f2009-12-16 01:14:31 +0300316#define PLPPAR1_UART0_BIT_MASK 0x00000fc0
317#define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80
318#define PLPDIR1_UART0_BIT_MASK 0x00000fc0
319#define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80
Haiying Wang765547d2009-03-27 17:02:45 -0400320
321/*
322 * General PCI
323 * Memory Addresses are mapped 1-1. I/O is mapped from 0
324 */
Kumar Gala94f2bc42010-12-17 10:18:07 -0600325#define CONFIG_SYS_PCIE1_NAME "Slot"
Haiying Wang765547d2009-03-27 17:02:45 -0400326#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
327#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
328#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
329#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
330#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
331#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
332#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
333#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
334
Kumar Galae5fe96b2011-01-04 18:04:01 -0600335#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000
336#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000
337#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS
338#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
Haiying Wang765547d2009-03-27 17:02:45 -0400339
340#ifdef CONFIG_QE
341/*
342 * QE UEC ethernet configuration
343 */
Haiying Wangf82107f2009-05-20 12:30:37 -0400344#define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */
345#undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */
Haiying Wang765547d2009-03-27 17:02:45 -0400346
347#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
348#define CONFIG_UEC_ETH
Kim Phillips78b7a8e2010-07-26 18:34:57 -0500349#define CONFIG_ETHPRIME "UEC0"
Haiying Wang765547d2009-03-27 17:02:45 -0400350#define CONFIG_PHY_MODE_NEED_CHANGE
351
352#define CONFIG_UEC_ETH1 /* GETH1 */
353#define CONFIG_HAS_ETH0
354
355#ifdef CONFIG_UEC_ETH1
356#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
357#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
Haiying Wangf82107f2009-05-20 12:30:37 -0400358#if defined(CONFIG_SYS_UCC_RGMII_MODE)
Haiying Wang765547d2009-03-27 17:02:45 -0400359#define CONFIG_SYS_UEC1_TX_CLK QE_CLK12
360#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
361#define CONFIG_SYS_UEC1_PHY_ADDR 7
Andy Fleming865ff852011-04-13 00:37:12 -0500362#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
Heiko Schocher582c55a2010-01-20 09:04:28 +0100363#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
Haiying Wangf82107f2009-05-20 12:30:37 -0400364#elif defined(CONFIG_SYS_UCC_RMII_MODE)
365#define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */
366#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
367#define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */
Andy Fleming865ff852011-04-13 00:37:12 -0500368#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
Heiko Schocher582c55a2010-01-20 09:04:28 +0100369#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
Haiying Wangf82107f2009-05-20 12:30:37 -0400370#endif /* CONFIG_SYS_UCC_RGMII_MODE */
371#endif /* CONFIG_UEC_ETH1 */
Haiying Wang765547d2009-03-27 17:02:45 -0400372
373#define CONFIG_UEC_ETH2 /* GETH2 */
374#define CONFIG_HAS_ETH1
375
376#ifdef CONFIG_UEC_ETH2
377#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
378#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
Haiying Wangf82107f2009-05-20 12:30:37 -0400379#if defined(CONFIG_SYS_UCC_RGMII_MODE)
Haiying Wang765547d2009-03-27 17:02:45 -0400380#define CONFIG_SYS_UEC2_TX_CLK QE_CLK17
381#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
382#define CONFIG_SYS_UEC2_PHY_ADDR 1
Andy Fleming865ff852011-04-13 00:37:12 -0500383#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
Heiko Schocher582c55a2010-01-20 09:04:28 +0100384#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
Haiying Wangf82107f2009-05-20 12:30:37 -0400385#elif defined(CONFIG_SYS_UCC_RMII_MODE)
386#define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */
387#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
388#define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */
Andy Fleming865ff852011-04-13 00:37:12 -0500389#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
Heiko Schocher582c55a2010-01-20 09:04:28 +0100390#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
Haiying Wangf82107f2009-05-20 12:30:37 -0400391#endif /* CONFIG_SYS_UCC_RGMII_MODE */
392#endif /* CONFIG_UEC_ETH2 */
Haiying Wang765547d2009-03-27 17:02:45 -0400393
Haiying Wang750098d2009-05-20 12:30:36 -0400394#define CONFIG_UEC_ETH3 /* GETH3 */
395#define CONFIG_HAS_ETH2
396
397#ifdef CONFIG_UEC_ETH3
398#define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */
399#define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE
Haiying Wangf82107f2009-05-20 12:30:37 -0400400#if defined(CONFIG_SYS_UCC_RGMII_MODE)
Haiying Wang750098d2009-05-20 12:30:36 -0400401#define CONFIG_SYS_UEC3_TX_CLK QE_CLK12
402#define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH
403#define CONFIG_SYS_UEC3_PHY_ADDR 2
Andy Fleming865ff852011-04-13 00:37:12 -0500404#define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
Heiko Schocher582c55a2010-01-20 09:04:28 +0100405#define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000
Haiying Wangf82107f2009-05-20 12:30:37 -0400406#elif defined(CONFIG_SYS_UCC_RMII_MODE)
407#define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */
408#define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH
409#define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */
Andy Fleming865ff852011-04-13 00:37:12 -0500410#define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
Heiko Schocher582c55a2010-01-20 09:04:28 +0100411#define CONFIG_SYS_UEC3_INTERFACE_SPEED 100
Haiying Wangf82107f2009-05-20 12:30:37 -0400412#endif /* CONFIG_SYS_UCC_RGMII_MODE */
413#endif /* CONFIG_UEC_ETH3 */
Haiying Wang750098d2009-05-20 12:30:36 -0400414
415#define CONFIG_UEC_ETH4 /* GETH4 */
416#define CONFIG_HAS_ETH3
417
418#ifdef CONFIG_UEC_ETH4
419#define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */
420#define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE
Haiying Wangf82107f2009-05-20 12:30:37 -0400421#if defined(CONFIG_SYS_UCC_RGMII_MODE)
Haiying Wang750098d2009-05-20 12:30:36 -0400422#define CONFIG_SYS_UEC4_TX_CLK QE_CLK17
423#define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH
424#define CONFIG_SYS_UEC4_PHY_ADDR 3
Andy Fleming865ff852011-04-13 00:37:12 -0500425#define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
Heiko Schocher582c55a2010-01-20 09:04:28 +0100426#define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000
Haiying Wangf82107f2009-05-20 12:30:37 -0400427#elif defined(CONFIG_SYS_UCC_RMII_MODE)
428#define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */
429#define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH
430#define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */
Andy Fleming865ff852011-04-13 00:37:12 -0500431#define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
Heiko Schocher582c55a2010-01-20 09:04:28 +0100432#define CONFIG_SYS_UEC4_INTERFACE_SPEED 100
Haiying Wangf82107f2009-05-20 12:30:37 -0400433#endif /* CONFIG_SYS_UCC_RGMII_MODE */
434#endif /* CONFIG_UEC_ETH4 */
Haiying Wang3bd8e532009-05-20 12:30:41 -0400435
436#undef CONFIG_UEC_ETH6 /* GETH6 */
437#define CONFIG_HAS_ETH5
438
439#ifdef CONFIG_UEC_ETH6
440#define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */
441#define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE
442#define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE
443#define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH
444#define CONFIG_SYS_UEC6_PHY_ADDR 4
Andy Fleming865ff852011-04-13 00:37:12 -0500445#define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
Heiko Schocher582c55a2010-01-20 09:04:28 +0100446#define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000
Haiying Wang3bd8e532009-05-20 12:30:41 -0400447#endif /* CONFIG_UEC_ETH6 */
448
449#undef CONFIG_UEC_ETH8 /* GETH8 */
450#define CONFIG_HAS_ETH7
451
452#ifdef CONFIG_UEC_ETH8
453#define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */
454#define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE
455#define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE
456#define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH
457#define CONFIG_SYS_UEC8_PHY_ADDR 6
Andy Fleming865ff852011-04-13 00:37:12 -0500458#define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
Heiko Schocher582c55a2010-01-20 09:04:28 +0100459#define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000
Haiying Wang3bd8e532009-05-20 12:30:41 -0400460#endif /* CONFIG_UEC_ETH8 */
461
Haiying Wang765547d2009-03-27 17:02:45 -0400462#endif /* CONFIG_QE */
463
464#if defined(CONFIG_PCI)
465
Haiying Wang765547d2009-03-27 17:02:45 -0400466#define CONFIG_PCI_PNP /* do pci plug-and-play */
467
468#undef CONFIG_EEPRO100
469#undef CONFIG_TULIP
Kumar Gala16855ec2010-11-09 23:19:50 -0600470#define CONFIG_E1000 /* Define e1000 pci Ethernet card */
Haiying Wang765547d2009-03-27 17:02:45 -0400471
472#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
473
474#endif /* CONFIG_PCI */
475
Haiying Wang765547d2009-03-27 17:02:45 -0400476/*
477 * Environment
478 */
Liu Yu674ef7b2010-01-18 19:03:28 +0800479#if defined(CONFIG_SYS_RAMBOOT)
480#if defined(CONFIG_RAMBOOT_NAND)
481#define CONFIG_ENV_IS_IN_NAND 1
482#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
483#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
484#endif
485#else
Haiying Wang765547d2009-03-27 17:02:45 -0400486#define CONFIG_ENV_IS_IN_FLASH 1
Haiying Wangfb279492009-06-04 16:12:39 -0400487#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Haiying Wang1b8e4fa2010-09-29 13:44:14 -0400488#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
489#define CONFIG_ENV_SIZE 0x2000
Liu Yu674ef7b2010-01-18 19:03:28 +0800490#endif
Haiying Wang765547d2009-03-27 17:02:45 -0400491
492#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
493#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
494
495/* QE microcode/firmware address */
Timur Tabif2717b42011-11-22 09:21:25 -0600496#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
497#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xfff00000
Haiying Wang765547d2009-03-27 17:02:45 -0400498
499/*
500 * BOOTP options
501 */
502#define CONFIG_BOOTP_BOOTFILESIZE
503#define CONFIG_BOOTP_BOOTPATH
504#define CONFIG_BOOTP_GATEWAY
505#define CONFIG_BOOTP_HOSTNAME
506
507
508/*
509 * Command line configuration.
510 */
511#include <config_cmd_default.h>
512
513#define CONFIG_CMD_PING
514#define CONFIG_CMD_I2C
515#define CONFIG_CMD_MII
516#define CONFIG_CMD_ELF
517#define CONFIG_CMD_IRQ
518#define CONFIG_CMD_SETEXPR
Becky Bruce199e2622010-06-17 11:37:25 -0500519#define CONFIG_CMD_REGINFO
Haiying Wang765547d2009-03-27 17:02:45 -0400520
521#if defined(CONFIG_PCI)
522 #define CONFIG_CMD_PCI
523#endif
524
525
526#undef CONFIG_WATCHDOG /* watchdog disabled */
527
Anton Vorontsov7f52ed52009-10-15 17:47:06 +0400528#define CONFIG_MMC 1
529
530#ifdef CONFIG_MMC
531#define CONFIG_FSL_ESDHC
Chenhui Zhaoa6da8b82011-01-04 17:23:05 +0800532#define CONFIG_FSL_ESDHC_PIN_MUX
Anton Vorontsov7f52ed52009-10-15 17:47:06 +0400533#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
534#define CONFIG_CMD_MMC
535#define CONFIG_GENERIC_MMC
536#define CONFIG_CMD_EXT2
537#define CONFIG_CMD_FAT
538#define CONFIG_DOS_PARTITION
539#endif
540
Haiying Wang765547d2009-03-27 17:02:45 -0400541/*
542 * Miscellaneous configurable options
543 */
Kim Phillips5be58f52010-07-14 19:47:18 -0500544#define CONFIG_SYS_LONGHELP /* undef to save memory */
545#define CONFIG_CMDLINE_EDITING /* Command-line editing */
546#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Haiying Wang765547d2009-03-27 17:02:45 -0400547#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Haiying Wang765547d2009-03-27 17:02:45 -0400548#if defined(CONFIG_CMD_KGDB)
549#define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */
550#else
551#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
552#endif
553#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
554 /* Print Buffer Size */
555#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
556#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
557 /* Boot Argument Buffer Size */
Haiying Wang765547d2009-03-27 17:02:45 -0400558
559/*
560 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500561 * have to be in the first 64 MB of memory, since this is
Haiying Wang765547d2009-03-27 17:02:45 -0400562 * the maximum mapped by the Linux kernel during initialization.
563 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500564#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
565#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Haiying Wang765547d2009-03-27 17:02:45 -0400566
Haiying Wang765547d2009-03-27 17:02:45 -0400567#if defined(CONFIG_CMD_KGDB)
568#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
569#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
570#endif
571
572/*
573 * Environment Configuration
574 */
575#define CONFIG_HOSTNAME mpc8569mds
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000576#define CONFIG_ROOTPATH "/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000577#define CONFIG_BOOTFILE "your.uImage"
Haiying Wang765547d2009-03-27 17:02:45 -0400578
579#define CONFIG_SERVERIP 192.168.1.1
580#define CONFIG_GATEWAYIP 192.168.1.1
581#define CONFIG_NETMASK 255.255.255.0
582
583#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
584
585#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
586#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
587
588#define CONFIG_BAUDRATE 115200
589
590#define CONFIG_EXTRA_ENV_SETTINGS \
591 "netdev=eth0\0" \
592 "consoledev=ttyS0\0" \
593 "ramdiskaddr=600000\0" \
594 "ramdiskfile=your.ramdisk.u-boot\0" \
595 "fdtaddr=400000\0" \
596 "fdtfile=your.fdt.dtb\0" \
597 "nfsargs=setenv bootargs root=/dev/nfs rw " \
598 "nfsroot=$serverip:$rootpath " \
599 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
600 "console=$consoledev,$baudrate $othbootargs\0" \
601 "ramargs=setenv bootargs root=/dev/ram rw " \
602 "console=$consoledev,$baudrate $othbootargs\0" \
603
604#define CONFIG_NFSBOOTCOMMAND \
605 "run nfsargs;" \
606 "tftp $loadaddr $bootfile;" \
607 "tftp $fdtaddr $fdtfile;" \
608 "bootm $loadaddr - $fdtaddr"
609
610#define CONFIG_RAMBOOTCOMMAND \
611 "run ramargs;" \
612 "tftp $ramdiskaddr $ramdiskfile;" \
613 "tftp $loadaddr $bootfile;" \
614 "bootm $loadaddr $ramdiskaddr"
615
616#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
617
618#endif /* __CONFIG_H */